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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:10:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:10:07 +0200 |
| commit | 1f62927ba89abc0fd43b1fceaa3c960252b05a26 (patch) | |
| tree | 7abfc60aa64cfb54647c421b2519409bbc2256b9 | |
| parent | 6b16e955ce1b41e88f825de3e9922ca11dd1037d (diff) | |
| download | ghdl-1f62927ba89abc0fd43b1fceaa3c960252b05a26.tar.gz ghdl-1f62927ba89abc0fd43b1fceaa3c960252b05a26.tar.bz2 ghdl-1f62927ba89abc0fd43b1fceaa3c960252b05a26.zip | |
synth: minor refactoring.
| -rw-r--r-- | src/synth/synth-insts.adb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index d92766ba6..656db9e58 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -644,14 +644,13 @@ package body Synth.Insts is procedure Create_Input_Wire (Self_Inst : Instance; Inter : Node; - Idx : in out Port_Idx; + Idx : Port_Idx; Val : Value_Acc) is begin case Val.Kind is when Value_Wire => Val.W := Alloc_Wire (Wire_Input, Inter); Set_Wire_Gate (Val.W, Get_Output (Self_Inst, Idx)); - Idx := Idx + 1; when others => raise Internal_Error; end case; @@ -659,7 +658,7 @@ package body Synth.Insts is procedure Create_Output_Wire (Self_Inst : Instance; Inter : Node; - Idx : in out Port_Idx; + Idx : Port_Idx; Val : Value_Acc) is Value : Net; @@ -677,7 +676,6 @@ package body Synth.Insts is Inp := Get_Input (Self_Inst, Idx); Connect (Inp, Value); Set_Wire_Gate (Val.W, Value); - Idx := Idx + 1; when others => raise Internal_Error; end case; @@ -772,10 +770,12 @@ package body Synth.Insts is when Port_In => Create_Input_Wire (Self_Inst, Inter, Nbr_Inputs, Get_Value (Syn_Inst, Inter)); + Nbr_Inputs := Nbr_Inputs + 1; when Port_Out | Port_Inout => Create_Output_Wire (Self_Inst, Inter, Nbr_Outputs, Get_Value (Syn_Inst, Inter)); + Nbr_Outputs := Nbr_Outputs + 1; end case; Inter := Get_Chain (Inter); end loop; |