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-rw-r--r--testsuite/issues/issue159/repro.vhdl16
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/issues/issue159/repro.vhdl b/testsuite/issues/issue159/repro.vhdl
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+++ b/testsuite/issues/issue159/repro.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+ port (i : std_logic;
+ o : out std_logic);
+end;
+
+architecture behav of repro is
+begin
+ process(i)
+ variable v : std_logic;
+ begin
+ o <= i or v;
+ end process;
+end behav;