testsuite: add test from ghdl/ghdl#1307

6 files changed, 432 insertions, 0 deletions

diff --git a/testsuite/ghdl-issues/issue1307/NexysVideo.xdc b/testsuite/ghdl-issues/issue1307/NexysVideo.xdc
new file mode 100644
index 0000000..75e7c49
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1307/NexysVideo.xdc
@@ -0,0 +1,72 @@
+#------------------------------------------------------------------------------------ 

+# HDMI and clock Constraints for the Digilent Nexys Video FPGA development board.

+#------------------------------------------------------------------------------------ 

+

+##Clock Signal

+set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk100 }];

+    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100]

+    

+##HDMI in

+create_clock -add -name hdmi_clk -period 6.7 -waveform {0 5} [get_ports hdmi_rx_clk_p]

+

+set_property -dict { PACKAGE_PIN AA5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec

+set_property -dict { PACKAGE_PIN W4    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n

+set_property -dict { PACKAGE_PIN V4    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p

+set_property -dict { PACKAGE_PIN AB12  IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa

+set_property -dict { PACKAGE_PIN Y4    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl

+set_property -dict { PACKAGE_PIN AB5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda

+set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen

+set_property -dict { PACKAGE_PIN AA3   IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]

+set_property -dict { PACKAGE_PIN Y3    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]

+set_property -dict { PACKAGE_PIN Y2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]

+set_property -dict { PACKAGE_PIN W2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]

+set_property -dict { PACKAGE_PIN V2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]

+set_property -dict { PACKAGE_PIN U2    IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]

+

+

+##HDMI out

+set_property -dict { PACKAGE_PIN AA4   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec

+set_property -dict { PACKAGE_PIN U1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n

+set_property -dict { PACKAGE_PIN T1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p

+set_property -dict { PACKAGE_PIN AB13  IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd

+set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl

+set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda

+set_property -dict { PACKAGE_PIN Y1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]

+set_property -dict { PACKAGE_PIN W1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]

+set_property -dict { PACKAGE_PIN AB1   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]

+set_property -dict { PACKAGE_PIN AA1   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]

+set_property -dict { PACKAGE_PIN AB2   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]

+set_property -dict { PACKAGE_PIN AB3   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]

+

+# DEBUG on JA

+set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1]

+set_property -dict { PACKAGE_PIN AB21  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2]

+set_property -dict { PACKAGE_PIN AB20  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]

+set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]

+set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]

+set_property -dict { PACKAGE_PIN AA21  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8]

+set_property -dict { PACKAGE_PIN AA20  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]

+set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10

+

+##Switches

+set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS25 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]

+set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS25 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]

+set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS25 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]

+set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS25 } [get_ports { sw[3] }]; #IO_L24N_T3_16 Sch=sw[3]

+set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS25 } [get_ports { sw[4] }]; #IO_L6P_T0_15 Sch=sw[4]

+set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS25 } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]

+set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS25 } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]

+set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS25 } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]

+

+##LEDs

+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { led[0] }]; #IO_L15P_T2_DQS_13 Sch=led[0]

+set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS25 } [get_ports { led[1] }]; #IO_L15N_T2_DQS_13 Sch=led[1]

+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS25 } [get_ports { led[2] }]; #IO_L17P_T2_13 Sch=led[2]

+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS25 } [get_ports { led[3] }]; #IO_L17N_T2_13 Sch=led[3]

+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS25 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_13 Sch=led[4]

+set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS25 } [get_ports { led[5] }]; #IO_L16N_T2_13 Sch=led[5]

+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS25 } [get_ports { led[6] }]; #IO_L16P_T2_13 Sch=led[6]

+set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]

+

+##UART

+set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports { rs232_tx }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out

diff --git a/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd b/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd
new file mode 100644
index 0000000..c14b67b
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd
@@ -0,0 +1,23 @@
+library IEEE;

+use IEEE.STD_LOGIC_1164.ALL;

+use IEEE.NUMERIC_STD.ALL;

+

+entity conversion_to_RGB is

+    port ( clk      : in std_Logic;

+           in_V     : in std_logic_vector(11 downto 0);

+           in_W     : in std_logic_vector(11 downto 0);

+

+           out_G     : out std_logic_vector(11 downto 0);

+           out_R     : out std_logic_vector(11 downto 0));

+end entity;

+

+architecture Behavioral of conversion_to_RGB is

+begin

+clk_proc: process(clk)

+   begin

+      if rising_edge(clk) then

+	out_G <= in_V;

+	out_R <= in_W;

+      end if;

+   end process;

+end architecture;

diff --git a/testsuite/ghdl-issues/issue1307/hdmi_design.vhd b/testsuite/ghdl-issues/issue1307/hdmi_design.vhd
new file mode 100644
index 0000000..8ed43b3
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1307/hdmi_design.vhd
@@ -0,0 +1,210 @@
+library IEEE;

+use IEEE.STD_LOGIC_1164.ALL;

+

+entity hdmi_design is

+    Port ( 

+        clk100    : in STD_LOGIC;

+        -- Control signals

+        led           : out   std_logic_vector(7 downto 0) :=(others => '0');

+        sw            : in    std_logic_vector(7 downto 0) :=(others => '0');

+        debug_pmod    : out   std_logic_vector(7 downto 0) :=(others => '0');

+

+        --HDMI input signals

+        hdmi_rx_cec   : inout std_logic;

+        hdmi_rx_hpa   : out   std_logic;

+        hdmi_rx_scl   : in    std_logic;

+        hdmi_rx_sda   : inout std_logic;

+        hdmi_rx_txen  : out   std_logic;

+        hdmi_rx_clk_n : in    std_logic;

+        hdmi_rx_clk_p : in    std_logic;

+        hdmi_rx_n     : in    std_logic_vector(2 downto 0);

+        hdmi_rx_p     : in    std_logic_vector(2 downto 0);

+

+        --- HDMI out

+        hdmi_tx_cec   : inout std_logic;

+        hdmi_tx_clk_n : out   std_logic;

+        hdmi_tx_clk_p : out   std_logic;

+        hdmi_tx_hpd   : in    std_logic;

+        hdmi_tx_rscl  : inout std_logic;

+        hdmi_tx_rsda  : inout std_logic;

+        hdmi_tx_p     : out   std_logic_vector(2 downto 0);

+        hdmi_tx_n     : out   std_logic_vector(2 downto 0);

+        -- For dumping symbols

+        rs232_tx     : out std_logic      

+    );

+end hdmi_design;

+

+architecture Behavioral of hdmi_design is

+    component hdmi_io is

+    Port ( 

+        clk100    : in STD_LOGIC;

+        -------------------------------

+        -- Control signals

+        -------------------------------

+        clock_locked  : out std_logic;

+        data_synced   : out std_logic;

+        debug         : out std_logic_vector(7 downto 0);        

+        -------------------------------

+        --HDMI input signals

+        -------------------------------

+        hdmi_rx_cec   : inout std_logic;

+        hdmi_rx_hpa   : out   std_logic;

+        hdmi_rx_scl   : in    std_logic;

+        hdmi_rx_sda   : inout std_logic;

+        hdmi_rx_txen  : out   std_logic;

+        hdmi_rx_clk_n : in    std_logic;

+        hdmi_rx_clk_p : in    std_logic;

+        hdmi_rx_n     : in    std_logic_vector(2 downto 0);

+        hdmi_rx_p     : in    std_logic_vector(2 downto 0);

+

+        -------------

+        -- HDMI out

+        -------------

+        hdmi_tx_cec   : inout std_logic;

+        hdmi_tx_clk_n : out   std_logic;

+        hdmi_tx_clk_p : out   std_logic;

+        hdmi_tx_hpd   : in    std_logic;

+        hdmi_tx_rscl  : inout std_logic;

+        hdmi_tx_rsda  : inout std_logic;

+        hdmi_tx_p     : out   std_logic_vector(2 downto 0);

+        hdmi_tx_n     : out   std_logic_vector(2 downto 0);

+

+        pixel_clk     : out std_logic;

+        -------------------------------

+        -- VGA data recovered from HDMI

+        -------------------------------

+        in_hdmi_detected : out std_logic;

+        in_blank        : out std_logic;

+        in_hsync        : out std_logic;

+        in_vsync        : out std_logic;

+        in_red          : out std_logic_vector(7 downto 0);

+        in_green        : out std_logic_vector(7 downto 0);

+        in_blue         : out std_logic_vector(7 downto 0);

+        is_interlaced   : out std_logic;

+        is_second_field : out std_logic;

+            

+        -------------------------------------

+        -- Audio Levels

+        -------------------------------------

+        audio_channel : out std_logic_vector(2 downto 0);

+        audio_de      : out std_logic;

+        audio_sample  : out std_logic_vector(23 downto 0);

+        

+        -----------------------------------

+        -- VGA data to be converted to HDMI

+        -----------------------------------

+        out_blank     : in  std_logic;

+        out_hsync     : in  std_logic;

+        out_vsync     : in  std_logic;

+        out_red       : in  std_logic_vector(7 downto 0);

+        out_green     : in  std_logic_vector(7 downto 0);

+        out_blue      : in  std_logic_vector(7 downto 0);

+        -----------------------------------

+        -- For symbol dump or retransmit

+        -----------------------------------

+        symbol_sync  : out std_logic; -- indicates a fixed reference point in the frame.

+        symbol_ch0   : out std_logic_vector(9 downto 0);

+        symbol_ch1   : out std_logic_vector(9 downto 0);

+        symbol_ch2   : out std_logic_vector(9 downto 0)

+    );

+    end component;

+    signal symbol_sync  : std_logic;

+    signal symbol_ch0   : std_logic_vector(9 downto 0);

+    signal symbol_ch1   : std_logic_vector(9 downto 0);

+    signal symbol_ch2   : std_logic_vector(9 downto 0);

+

+    signal pixel_clk : std_logic;

+    signal in_blank  : std_logic;

+    signal in_hsync  : std_logic;

+    signal in_vsync  : std_logic;

+    signal in_red    : std_logic_vector(7 downto 0);

+    signal in_green  : std_logic_vector(7 downto 0);

+    signal in_blue   : std_logic_vector(7 downto 0);

+    signal is_interlaced   : std_logic;

+    signal is_second_field : std_logic;

+    signal out_blank : std_logic;

+    signal out_hsync : std_logic;

+    signal out_vsync : std_logic;

+    signal out_red   : std_logic_vector(7 downto 0);

+    signal out_green : std_logic_vector(7 downto 0);

+    signal out_blue  : std_logic_vector(7 downto 0);

+

+    signal audio_channel : std_logic_vector(2 downto 0);

+    signal audio_de      : std_logic;

+    signal audio_sample  : std_logic_vector(23 downto 0);

+

+    signal debug : std_logic_vector(7 downto 0);

+begin

+--    debug_pmod <= debug;    

+--    led        <= debug;

+    

+i_hdmi_io: hdmi_io port map ( 

+        clk100        => clk100,

+        ---------------------

+        -- Control signals

+        ---------------------

+        clock_locked     => open,

+        data_synced      => open,

+        debug            => debug,

+        ---------------------

+        -- HDMI input signals

+        ---------------------

+        hdmi_rx_cec   => hdmi_rx_cec,

+        hdmi_rx_hpa   => hdmi_rx_hpa,

+        hdmi_rx_scl   => hdmi_rx_scl,

+        hdmi_rx_sda   => hdmi_rx_sda,

+        hdmi_rx_txen  => hdmi_rx_txen,

+        hdmi_rx_clk_n => hdmi_rx_clk_n,

+        hdmi_rx_clk_p => hdmi_rx_clk_p,

+        hdmi_rx_p     => hdmi_rx_p,

+        hdmi_rx_n     => hdmi_rx_n,

+

+        ----------------------

+        -- HDMI output signals

+        ----------------------

+        hdmi_tx_cec   => hdmi_tx_cec,

+        hdmi_tx_clk_n => hdmi_tx_clk_n,

+        hdmi_tx_clk_p => hdmi_tx_clk_p,

+        hdmi_tx_hpd   => hdmi_tx_hpd,

+        hdmi_tx_rscl  => hdmi_tx_rscl,

+        hdmi_tx_rsda  => hdmi_tx_rsda,

+        hdmi_tx_p     => hdmi_tx_p,

+        hdmi_tx_n     => hdmi_tx_n,     

+

+        

+        pixel_clk => pixel_clk,

+        -------------------------------

+        -- VGA data recovered from HDMI

+        -------------------------------

+        in_blank        => in_blank,

+        in_hsync        => in_hsync,

+        in_vsync        => in_vsync,

+        in_red          => in_red,

+        in_green        => in_green,

+        in_blue         => in_blue,

+        is_interlaced   => is_interlaced,

+        is_second_field => is_second_field,

+

+        -----------------------------------

+        -- For symbol dump or retransmit

+        -----------------------------------

+        audio_channel => audio_channel,

+        audio_de      => audio_de,

+        audio_sample  => audio_sample,

+        

+        -----------------------------------

+        -- VGA data to be converted to HDMI

+        -----------------------------------

+        out_blank => out_blank,

+        out_hsync => out_hsync,

+        out_vsync => out_vsync,

+        out_red   => out_red,

+        out_green => out_green,

+        out_blue  => out_blue,

+        

+        symbol_sync  => symbol_sync, 

+        symbol_ch0   => symbol_ch0,

+        symbol_ch1   => symbol_ch1,

+        symbol_ch2   => symbol_ch2

+    );

+end Behavioral;

diff --git a/testsuite/ghdl-issues/issue1307/hdmi_io.vhd b/testsuite/ghdl-issues/issue1307/hdmi_io.vhd
new file mode 100644
index 0000000..ded6a12
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1307/hdmi_io.vhd
@@ -0,0 +1,110 @@
+library IEEE;

+use IEEE.STD_LOGIC_1164.ALL;

+

+entity hdmi_io is

+    port (

+        clk100        : in STD_LOGIC;

+        -------------------------------

+        -- Control signals

+        -------------------------------

+        clock_locked   : out std_logic;

+        data_synced    : out std_logic;

+        debug          : out std_logic_vector(7 downto 0);        

+        

+        -------------------------------

+        --HDMI input signals

+        -------------------------------

+        hdmi_rx_cec   : inout std_logic;

+        hdmi_rx_hpa   : out   std_logic;

+        hdmi_rx_scl   : in    std_logic;

+        hdmi_rx_sda   : inout std_logic;

+        hdmi_rx_txen  : out   std_logic;

+        hdmi_rx_clk_n : in    std_logic;

+        hdmi_rx_clk_p : in    std_logic;

+        hdmi_rx_n     : in    std_logic_vector(2 downto 0);

+        hdmi_rx_p     : in    std_logic_vector(2 downto 0);

+        

+        -------------

+        -- HDMI out

+        -------------

+        hdmi_tx_cec   : inout std_logic;

+        hdmi_tx_clk_n : out   std_logic;

+        hdmi_tx_clk_p : out   std_logic;

+        hdmi_tx_hpd   : in    std_logic;

+        hdmi_tx_rscl  : inout std_logic;

+        hdmi_tx_rsda  : inout std_logic;

+        hdmi_tx_p     : out   std_logic_vector(2 downto 0);

+        hdmi_tx_n     : out   std_logic_vector(2 downto 0);

+        

+        pixel_clk : out std_logic;

+        -------------------------------

+        -- VGA data recovered from HDMI

+        -------------------------------

+        in_hdmi_detected : out std_logic;

+        in_blank  : out std_logic;

+        in_hsync  : out std_logic;

+        in_vsync  : out std_logic;

+        in_red    : out std_logic_vector(7 downto 0);

+        in_green  : out std_logic_vector(7 downto 0);

+        in_blue   : out std_logic_vector(7 downto 0);

+        is_interlaced   : out std_logic;

+        is_second_field : out std_logic;

+        

+        -----------------------------------

+        -- VGA data to be converted to HDMI

+        -----------------------------------

+        out_blank : in  std_logic;

+        out_hsync : in  std_logic;

+        out_vsync : in  std_logic;

+        out_red   : in  std_logic_vector(7 downto 0);

+        out_green : in  std_logic_vector(7 downto 0);

+        out_blue  : in  std_logic_vector(7 downto 0);

+       -------------------------------------

+        -- Audio Levels

+        -------------------------------------

+        audio_channel : out std_logic_vector(2 downto 0);

+        audio_de      : out std_logic;

+        audio_sample  : out std_logic_vector(23 downto 0);

+        

+        -----------------------------------

+        -- For symbol dump or retransmit

+        -----------------------------------

+        symbol_sync  : out std_logic; -- indicates a fixed reference point in the frame.

+        symbol_ch0   : out std_logic_vector(9 downto 0);

+        symbol_ch1   : out std_logic_vector(9 downto 0);

+        symbol_ch2   : out std_logic_vector(9 downto 0)

+    );

+end entity;

+

+architecture Behavioral of hdmi_io is

+

+    signal fourfourfour_V     : std_logic_vector(11 downto 0);

+    signal fourfourfour_W     : std_logic_vector(11 downto 0);

+

+    component conversion_to_RGB is

+        port ( clk            : in std_Logic;

+               in_V           : in std_logic_vector(11 downto 0);

+               in_W           : in std_logic_vector(11 downto 0);

+               out_R          : out std_logic_vector(11 downto 0);

+               out_G          : out std_logic_vector(11 downto 0)

+          );

+    end component;

+

+    signal rgb_R     : std_logic_vector(11 downto 0);

+    signal rgb_G     : std_logic_vector(11 downto 0);

+begin

+

+i_conversion_to_RGB: conversion_to_RGB 

+    port map (

+           clk              => clk100,

+           in_V             => fourfourfour_V,

+           in_W             => fourfourfour_W,

+           out_G            => rgb_G,

+           out_R            => rgb_R

+    );

+

+    in_green <= rgb_G(11 downto 4);

+    in_red   <= rgb_R(11 downto 4);

+

+

+end Behavioral;

diff --git a/testsuite/ghdl-issues/issue1307/run_vivado.tcl b/testsuite/ghdl-issues/issue1307/run_vivado.tcl
new file mode 100644
index 0000000..19e2624
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1307/run_vivado.tcl
@@ -0,0 +1,9 @@
+read_xdc NexysVideo.xdc
+read_edif hdmi_design.edif
+link_design -part xc7a35tcpg236-1 -top hdmi_design
+opt_design
+place_design
+route_design
+report_utilization
+report_timing
+write_bitstream -force example.bit
diff --git a/testsuite/ghdl-issues/issue1307/testsuite.sh b/testsuite/ghdl-issues/issue1307/testsuite.sh
new file mode 100755
index 0000000..8c96672
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1307/testsuite.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl hdmi_design.vhd hdmi_io.vhd conversion_to_RGB.vhd -e; synth_xilinx -flatten -edif hdmi_design.edif"
+
+echo OK