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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:32:49 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:32:49 +0100 |
| commit | 0833d3f90a29f0bce364833f20430968deeee0b7 (patch) | |
| tree | 4f91c24c02956fe435de2c079258cc76eb7324b0 /testsuite/issues/issue73/cell1.vhdl | |
| parent | 41222e9d1193dedc407158352f7180dc6d5ee655 (diff) | |
| download | ghdl-yosys-plugin-0833d3f90a29f0bce364833f20430968deeee0b7.tar.gz ghdl-yosys-plugin-0833d3f90a29f0bce364833f20430968deeee0b7.tar.bz2 ghdl-yosys-plugin-0833d3f90a29f0bce364833f20430968deeee0b7.zip | |
Add testcase for #73
Diffstat (limited to 'testsuite/issues/issue73/cell1.vhdl')
| -rw-r--r-- | testsuite/issues/issue73/cell1.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/issues/issue73/cell1.vhdl b/testsuite/issues/issue73/cell1.vhdl new file mode 100644 index 0000000..32a5358 --- /dev/null +++ b/testsuite/issues/issue73/cell1.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cell1 is + port ( + O: out std_logic + ); +end entity cell1; + +architecture rtl of cell1 is +begin + O <= '0'; +end architecture rtl; + |