after tidy

10 files changed, 563 insertions, 749 deletions

diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile
index b3ae3ea..bd2180e 100644
--- a/spartan6/hp_lcd_driver/Makefile
+++ b/spartan6/hp_lcd_driver/Makefile
@@ -45,7 +45,7 @@ XST_DIR=xst
 default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF}
 
 clean: 
-	/bin/rm -rf ${BUILD}
+	/bin/rm -rf ${BUILD} *.orig *~
 
 ${PRJ}: ${VSRCS} ${GEN_VSRCS}
 	mkdir -p ${BUILD}
@@ -98,197 +98,7 @@ ${BUILD}/%.vhd:%.xco
 
 
 tidy:
-	git diff --exit-code -s source	
+	git diff --exit-code -s ${VSRCS}	
 	for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
 
 
-#
-#
-##
-## Flags and option values that control the behavior of the Xilinx tools.
-## You can override these values in the makefile that includes this one.
-## Otherwise, the default values will be set as shown below.
-##
-#
-## Unless otherwise specified, the name of the design and the top-level
-## entity are derived from the name of the directory that contains the design.
-#DIR_SPACES  := $(subst /, ,$(CURDIR))
-#DIR_NAME    := $(word $(words $(DIR_SPACES)), $(DIR_SPACES))
-#DESIGN_NAME ?= $(DIR_NAME)
-#TOP_NAME    ?= $(DESIGN_NAME)
-#SYNTH_DIR   ?= .
-#SIM_DIR   ?= .
-#
-## Extract the part identifier from the project .npl file.
-#PART_TYPE        ?=            $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVICE)
-#PART_SPEED_GRADE ?= $(subst -,,$(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVSPEED))
-#PART_PACKAGE     ?=            $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVPKG)
-#PART             ?= $(PART_TYPE)-$(PART_SPEED_GRADE)-$(PART_PACKAGE)
-#
-## Flags common to both FPGA design flow.
-#INTSTYLE         ?= -intstyle silent      # call Xilinx tools in silent mode
-#XST_FLAGS        ?= $(INTSTYLE)           # most synthesis flags are specified in the .xst file
-#UCF_FILE         ?= $(DESIGN_NAME).ucf    # constraint/pin-assignment file
-#NGDBUILD_FLAGS   ?= $(INTSTYLE) -dd _ngo  # ngdbuild flags
-#NGDBUILD_FLAGS += $(if $(UCF_FILE),-uc,) $(UCF_FILE)         # append the UCF file option if it is specified 
-#
-## Flags for FPGA-specific tools.  These were extracted by looking in the
-## .cmd_log file after compiling the design with the WebPACK/ISE GUI.
-#MAP_FLAGS        ?= $(INTSTYLE) -cm area -pr b -c 100 -tx off
-#PAR_FLAGS        ?= $(INTSTYLE) -w -ol std -t 1
-#TRCE_FLAGS       ?= $(INTSTYLE) -e 3 -l 3
-#BITGEN_FLAGS     ?= $(INTSTYLE) -w        # most bitgen flags are specified in the .ut file
-#PROMGEN_FLAGS    ?= -u 0                  # flags that control the MCS/EXO file generation
-#
-## Determine the version of Xilinx ISE that is being used by reading it from the
-## readme.txt file in the top-level directory of the Xilinx software.
-#PROJNAV_DIR ?= .
-#
-#XST_FPGA_OPTIONS_FILE ?= $(PROJNAV_DIR)/$(DESIGN_NAME).xst
-#BITGEN_OPTIONS_FILE   ?= $(DESIGN_NAME).ut
-#XST_OPTIONS_FILE       = $(XST_FPGA_OPTIONS_FILE)
-#
-#
-#
-##
-## The following rules describe how to compile the design to an FPGA
-##
-#
-#HDL_FILES := $(foreach file,$(SRCS_SYNTH),$(SYNTH_DIR)/$(file))
-#SIM_FILES := $(foreach file,$(SRCS_SIM),$(SIM_DIR)/$(file))
-#
-## default target
-#all: bit
-#
-#
-## cleanup the source code to make it look nice
-#%.nice: %.vhd
-#	$(EMACS) -batch $< -f vhdl-beautify-buffer -f save-buffer
-#	$(RM) $<~
-#
-##PRJ FIle generation
-#%.prj:
-#	rm -f  $(DESIGN_NAME).prj;
-#	for file in $(HDL_FILES); do \
-#	echo "vhdl work $${file}" >> $(DESIGN_NAME).prj ; \
-#	done ;
-#
-#%.ut:
-#	cp -n $(UTILITY_DIR)/default.ut $(DESIGN_NAME).ut
-#
-#%.xst:
-#	cp -n $(UTILITY_DIR)/default.xst $(DESIGN_NAME).xst
-#
-#%.ucf:
-#	cp -n $(UTILITY_DIR)/default.ucf $(UCF_FILE)
-#
-#
-#
-#
-#
-## Synthesize the HDL files into an NGC file.  This rule is triggered if
-## any of the HDL files are changed or the synthesis options are changed.
-#%.ngc: $(HDL_FILES) $(XST_OPTIONS_FILE) $(DESIGN_NAME).prj $(DESIGN_NAME).ut
-#	$(SET_OPTION_VALUES) $(XST_OPTIONS_FILE) \
-#		"set -tmpdir $(PROJNAV_DIR)" \
-#		"-lso $(DESIGN_NAME).lso" \
-#		"-ifn $(DESIGN_NAME).prj" \
-#		"-ofn $(DESIGN_NAME)" \
-#		"-p $(PART)" \
-#		"-top $(TOP_NAME)" \
-#			> $(PROJNAV_DIR)/tmp.xst
-#	${ISE_BINDIR_64}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr
-#
-## Take the output of the synthesizer and create the NGD file.  This rule
-## will also be triggered if constraints file is changed.
-#%.ngd: %.ngc %.ucf
-#	${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd
-#
-## Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file.
-#%_map.ncd %.pcf: %.ngd
-#	${ISE_BINDIR_64}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf
-#
-## Place & route the mapped NCD file to create the final NCD file.
-#%.ncd: %_map.ncd %.pcf
-#	${ISE_BINDIR_64}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf
-#
-## Take the final NCD file and create an FPGA bitstream file.  This rule will also be
-## triggered if the bit generation options file is changed.
-#%.bit: %.ncd $(BITGEN_OPTIONS_FILE)
-#	${ISE_BINDIR_64}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd
-#
-## Convert a bitstream file into an MCS hex file that can be stored into Flash memory.
-#%.mcs: %.bit
-#	${ISE_BINDIR_64}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs
-#
-## Convert a bitstream file into an EXO hex file that can be stored into Flash memory.
-#%.exo: %.bit
-#	${ISE_BINDIR_64}/promgen $(PROMGEN_FLAGS) $*.bit -p exo
-#
-## Use .config suffix to trigger creation of a bit/svf file
-## depending upon whether an FPGA is the target device.
-#%.config: %.bit ;
-#
-## Create the FPGA timing report after place & route.
-#%.twr: %.ncd %.pcf
-#	${ISE_BINDIR_64}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf
-#
-## Use .timing suffix to trigger timing report creation.
-#%.timing: %.twr ;
-#
-## Preserve intermediate files.
-#.PRECIOUS: %.ngc %.ngd %_map.ncd %.ncd %.twr %.vm6 %.jed %.prj %.ut %.xst %.ucf
-#
-## Clean up after creating the configuration file.
-#%.clean:
-#	-$(RM) *.stx *.ucf.untf *.mrp *.nc1 *.ngm *.prm *.lfp
-#	-$(RM) *.placed_ncd_tracker *.routed_ncd_tracker
-#	-$(RM) *.pad_txt *.twx *.log *.vhd~ *.dhp *.jhd *.cel
-#	-$(RM) *.ngr *.ngc *.ngd *.syr *.bld *.pcf
-#	-$(RM) *_map.mrp *_map.ncd *_map.ngm *.ncd *.pad *.bit
-#	-$(RM) *.par *.xpi *_pad.csv *_pad.txt *.drc *.bgn *.lso *.npl
-#	-$(RM) *.xml *_build.xml *.rpt *.gyd *.mfd *.pnx *.xrpt *.ptwx *.twr *.srp
-#	-$(RM) *.vm6 *.jed *.err *.ER result.txt tmperr.err *.bak *.vhd~
-#	-$(RM) *.zip *_backup *.*log *.map *.unroutes *.html
-#	-$(RM) impactcmd.txt tmp.xst impact.run *.wlf transcript
-#	-$(RMDIR) xst _ngo *_html __projnav xlnx_auto_* work
-#
-## Clean everything.
-#%.distclean: %.clean
-#	-$(RM) *.prj
-#
-#%.impact : $(DESIGN_NAME).bit
-#	echo -e "setMode -bs \n\
-#	setCable -p auto \n\
-#	identify  \n\
-#	assignFile -p 1 -file $(DESIGN_NAME).bit \n\
-#	program -p 1 \n\
-#	quit \n" > impact.run
-#	${ISE_BINDIR_64}/impact -batch impact.run
-#
-##Simulation using ModelSIM
-#setlib:
-#	${ISE_BINDIR_64}/vlib work
-#
-#vsim-compile: setlib $(SIM_FILES) $(HDL_FILES)
-#	${ISE_BINDIR_64}/vcom $(HDL_FILES)  $(SIM_FILES)
-#
-#vsim: vsim-compile
-#	${ISE_BINDIR_64}/vsim  $(TESTBENCH_NAME)
-#
-#vsim-run: vsim-compile
-#	${ISE_BINDIR_64}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME)
-#
-##
-## Default targets for FPGA compilations.
-##
-#
-#config          : $(DESIGN_NAME).config
-#bit             : $(DESIGN_NAME).bit
-#mcs             : $(DESIGN_NAME).mcs
-#exo             : $(DESIGN_NAME).exo
-#timing          : $(DESIGN_NAME).timing
-#clean           : $(DESIGN_NAME).clean
-#distclean       : $(DESIGN_NAME).distclean
-#nice            : $(subst .vhd,.nice,$(HDL_FILES))
-#impact          : $(DESIGN_NAME).impact
diff --git a/spartan6/hp_lcd_driver/debounce.vhdl b/spartan6/hp_lcd_driver/debounce.vhdl
index 654a2f3..286367d 100644
--- a/spartan6/hp_lcd_driver/debounce.vhdl
+++ b/spartan6/hp_lcd_driver/debounce.vhdl
@@ -17,7 +17,7 @@ begin
 
     o <= output;
 
-    process (clk,flipflops,i)
+    process (clk, flipflops, i)
     begin
         if rising_edge(clk) then
             flipflops <= flipflops(flipflops'high-1 downto 0) & i;
diff --git a/spartan6/hp_lcd_driver/edge_det.vhdl b/spartan6/hp_lcd_driver/edge_det.vhdl
index 8cb38eb..2a592a5 100644
--- a/spartan6/hp_lcd_driver/edge_det.vhdl
+++ b/spartan6/hp_lcd_driver/edge_det.vhdl
@@ -14,7 +14,7 @@ architecture Behavioral of edge_det is
     signal last : std_logic := '0';
 begin
 
-    process(clk,last,sig) 
+    process(clk, last, sig)
     begin
         if rising_edge(clk) then
             last <= sig;
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index 0789102..7f52ca1 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -18,11 +18,11 @@
 --
 ----------------------------------------------------------------------------------
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
 use work.all;
 
-Library UNISIM;
+library UNISIM;
 use UNISIM.vcomponents.all;
 
 -- Uncomment the following library declaration if using
@@ -34,144 +34,144 @@ use UNISIM.vcomponents.all;
 --use UNISIM.VComponents.all;
 
 entity hp_lcd_driver is
-    generic (video_width     : natural := 2;
-	     addr_width      : natural := 18);
-    port ( clk_50m_in : in  STD_LOGIC;
-	   sys_rst_n : in STD_LOGIC;
-           video : in  std_logic_vector(video_width-1 downto 0);
-           hsync_in : in  STD_LOGIC;
-           vsync_in : in  STD_LOGIC;
-	   red_out : out STD_LOGIC;
-	   blue_out : out STD_LOGIC;
-	   green_out : out STD_LOGIC;
-	   hsync_out : out STD_LOGIC;
-	   vsync_out : out STD_LOGIC;
-           hdmi_c : out  STD_LOGIC;
-           hdmi_r : out  STD_LOGIC;
-           hdmi_g : out  STD_LOGIC;
-           hdmi_b : out  STD_LOGIC);
+    generic (video_width : natural := 2;
+             addr_width  : natural := 18);
+    port (clk_50m_in : in  std_logic;
+          sys_rst_n  : in  std_logic;
+          video      : in  std_logic_vector(video_width-1 downto 0);
+          hsync_in   : in  std_logic;
+          vsync_in   : in  std_logic;
+          red_out    : out std_logic;
+          blue_out   : out std_logic;
+          green_out  : out std_logic;
+          hsync_out  : out std_logic;
+          vsync_out  : out std_logic;
+          hdmi_c     : out std_logic;
+          hdmi_r     : out std_logic;
+          hdmi_g     : out std_logic;
+          hdmi_b     : out std_logic);
 end hp_lcd_driver;
 
 architecture Behavioral of hp_lcd_driver is
 
-signal wr_addr : std_logic_vector(addr_width-1 downto 0);
-signal wr_data : std_logic_vector(video_width-1 downto 0);
-signal wr_en : std_logic_vector(0 downto 0);
+    signal wr_addr : std_logic_vector(addr_width-1 downto 0);
+    signal wr_data : std_logic_vector(video_width-1 downto 0);
+    signal wr_en   : std_logic_vector(0 downto 0);
 
-signal rd_addr : std_logic_vector(addr_width-1 downto 0);
-signal rd_data : std_logic_vector(video_width-1 downto 0);
+    signal rd_addr : std_logic_vector(addr_width-1 downto 0);
+    signal rd_data : std_logic_vector(video_width-1 downto 0);
 
-signal red : std_logic_vector(7 downto 0);
-signal green : std_logic_vector(7 downto 0);
-signal blue : std_logic_vector(7 downto 0);
+    signal red   : std_logic_vector(7 downto 0);
+    signal green : std_logic_vector(7 downto 0);
+    signal blue  : std_logic_vector(7 downto 0);
 
 
-signal i_clk : std_logic;
-signal o_clk_5: std_logic;
-signal o_clk: std_logic;
-signal o_clk_n: std_logic;
+    signal i_clk   : std_logic;
+    signal o_clk_5 : std_logic;
+    signal o_clk   : std_logic;
+    signal o_clk_n : std_logic;
 
-signal clk_50m : std_logic;
+    signal clk_50m : std_logic;
 
-signal sys_rst : std_logic;
+    signal sys_rst : std_logic;
 
 begin
 
-sys_rst <= not sys_rst_n;
-
-clk_buf: BUFG
-port map (
-   I => clk_50m_in,
-   O => clk_50m
-);
-
-
-
-ipll:entity  work.pll_50_80
-	port map (
-		reset => sys_rst,
-		clk_50_in => clk_50m,
-		clk_80_out => i_clk
-	);
-
-opll:entity  work.pll_50_91_18
-	port map (
-		reset => sys_rst,
-		clk_50_in => clk_50m,
-		clk_91_666_out => o_clk_5,
-		clk_18_333_out => o_clk
-	);
-
-input0: entity work.input_stage
-		generic map(
-		video_width => video_width,
-		addr_width => addr_width,
-		clk_multiple => 4, 
-		phase => 2,
-		h_front_porch => 208,
-		h_active => 592,
-		v_front_porch => 2,
-		v_active => 384,
-		h_stride => 384,
-		v_stride => 1
-		)
-	port map (
-	  sys_rst_n => sys_rst_n,
-	clk => i_clk,
-	  video_in => video,
-	  hsync_in => hsync_in,
-	  vsync_in => vsync_in,
-	  video_out => wr_data,
-	  addr_out => wr_addr,
-	  wren_out => wr_en(0));
-
-vram0: entity work.vram
-	port map (
-	clka => i_clk,
-	wea => wr_en,
-	addra => wr_addr,
-	dina => wr_data,
-	clkb => o_clk,
-	addrb => rd_addr,
-	doutb => rd_data
-);
-
-
-output0: entity work.output_stage
+    sys_rst <= not sys_rst_n;
+
+    clk_buf : BUFG
+        port map (
+            I => clk_50m_in,
+            O => clk_50m
+            );
+
+
+
+    ipll : entity work.pll_50_80
+        port map (
+            reset      => sys_rst,
+            clk_50_in  => clk_50m,
+            clk_80_out => i_clk
+            );
+
+    opll : entity work.pll_50_91_18
+        port map (
+            reset          => sys_rst,
+            clk_50_in      => clk_50m,
+            clk_91_666_out => o_clk_5,
+            clk_18_333_out => o_clk
+            );
+
+    input0 : entity work.input_stage
+        generic map(
+            video_width   => video_width,
+            addr_width    => addr_width,
+            clk_multiple  => 4,
+            phase         => 2,
+            h_front_porch => 208,
+            h_active      => 592,
+            v_front_porch => 2,
+            v_active      => 384,
+            h_stride      => 384,
+            v_stride      => 1
+            )
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => i_clk,
+            video_in  => video,
+            hsync_in  => hsync_in,
+            vsync_in  => vsync_in,
+            video_out => wr_data,
+            addr_out  => wr_addr,
+            wren_out  => wr_en(0));
+
+    vram0 : entity work.vram
+        port map (
+            clka  => i_clk,
+            wea   => wr_en,
+            addra => wr_addr,
+            dina  => wr_data,
+            clkb  => o_clk,
+            addrb => rd_addr,
+            doutb => rd_data
+            );
+
+
+    output0 : entity work.output_stage
 
 -- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
-	generic map (
-		addr_width => addr_width,
-		h_active => 384,
-		h_sync_start => 400,
-		h_sync_end => 440,
-		h_total =>600,
-		v_active=>592,
-		v_sync_start=>593,
-		v_sync_end=>596,
-		v_total=>614,
-		h_stride => 1,
-		v_stride => 384
-	)
-	port map(
-		clk => o_clk,
-		sys_rst_n => sys_rst_n,
-	  	vsync_in => vsync_in,
-		red_in => red,
-		green_in=>green,
-		blue_in => blue,
-		addr_out => rd_addr,
-		red_out => red_out,
-		green_out => green_out,
-		blue_out => blue_out,
-		hsync_out => hsync_out,
-		vsync_out => vsync_out,
-		hdmi_r => hdmi_r,
-		hdmi_g => hdmi_g,
-		hdmi_b => hdmi_b,
-		hdmi_c => hdmi_c
-	);
-	
+        generic map (
+            addr_width   => addr_width,
+            h_active     => 384,
+            h_sync_start => 400,
+            h_sync_end   => 440,
+            h_total      => 600,
+            v_active     => 592,
+            v_sync_start => 593,
+            v_sync_end   => 596,
+            v_total      => 614,
+            h_stride     => 1,
+            v_stride     => 384
+            )
+        port map(
+            clk       => o_clk,
+            sys_rst_n => sys_rst_n,
+            vsync_in  => vsync_in,
+            red_in    => red,
+            green_in  => green,
+            blue_in   => blue,
+            addr_out  => rd_addr,
+            red_out   => red_out,
+            green_out => green_out,
+            blue_out  => blue_out,
+            hsync_out => hsync_out,
+            vsync_out => vsync_out,
+            hdmi_r    => hdmi_r,
+            hdmi_g    => hdmi_g,
+            hdmi_b    => hdmi_b,
+            hdmi_c    => hdmi_c
+            );
+
 
 end Behavioral;
 
diff --git a/spartan6/hp_lcd_driver/input_formatter.vhdl b/spartan6/hp_lcd_driver/input_formatter.vhdl
index 681795f..ef1cc0d 100644
--- a/spartan6/hp_lcd_driver/input_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/input_formatter.vhdl
@@ -1,45 +1,45 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
 
-ENTITY input_formatter IS
+entity input_formatter is
     generic (
-	     addr_width      : natural := 17;
-		clk_multiple : natural := 4;
-		phase : natural := 2;
-		h_front_porch : natural := 208;
-		h_active : natural := 592;
-		v_front_porch : natural := 2;
-		v_active : natural := 384;
-		h_stride : natural := 384;
-		v_stride : natural := 1);
-	PORT
-	(
-	  sys_rst_n : in std_logic;
-	  clk : in std_logic;
-	  hsync:in std_logic;
-	  vsync: in std_logic;
-	  addr_out : out std_logic_vector(addr_width-1 downto 0);
-	  wren_out : out std_logic
-	  );
-	  
-END input_formatter;
-
-
-ARCHITECTURE beh OF input_formatter IS
-
-   signal row_addr : std_logic_vector(addr_width-1 downto 0)	;
-   signal addr : std_logic_vector(addr_width-1 downto 0)	;
-   signal wren: std_logic;
-
- signal hsync_pe: std_logic;
- signal hsync_ne: std_logic;
-
- signal fp_counter:natural;
- signal active_counter:natural;
-
-		
+        addr_width    : natural := 17;
+        clk_multiple  : natural := 4;
+        phase         : natural := 2;
+        h_front_porch : natural := 208;
+        h_active      : natural := 592;
+        v_front_porch : natural := 2;
+        v_active      : natural := 384;
+        h_stride      : natural := 384;
+        v_stride      : natural := 1);
+    port
+        (
+            sys_rst_n : in  std_logic;
+            clk       : in  std_logic;
+            hsync     : in  std_logic;
+            vsync     : in  std_logic;
+            addr_out  : out std_logic_vector(addr_width-1 downto 0);
+            wren_out  : out std_logic
+            );
+
+end input_formatter;
+
+
+architecture beh of input_formatter is
+
+    signal row_addr : std_logic_vector(addr_width-1 downto 0);
+    signal addr     : std_logic_vector(addr_width-1 downto 0);
+    signal wren     : std_logic;
+
+    signal hsync_pe : std_logic;
+    signal hsync_ne : std_logic;
+
+    signal fp_counter     : natural;
+    signal active_counter : natural;
+
+
 begin
 
 
@@ -52,55 +52,55 @@ begin
 
 
 
-addr<= (others => '0');
+    addr <= (others => '0');
 
-addr_out <= addr;
-wren_out <= '0';
+    addr_out <= addr;
+    wren_out <= '0';
 
 
 ---- horizontal state machine
 --
---	process (sys_rst_n,p_clk,d_hsync,d_vsync)  begin
---	if sys_rst_n = '0' then
---		row_addr<=(others =>'0');
---		addr<=(others =>'0');
---		p_clk_div<=p_clk_multiple;
---		active_counter <=0;
---		fp_counter <=0;
---	elsif rising_edge(p_clk) then
---		if d_vsync='1' then
---			row_addr<=(others => '0');
---			addr<=(others => '0');
---			fp_counter <= front_porch;
---			active_counter <=hres;
---			p_clk_div <=p_clk_multiple;
---            	elsif pe_gsync ='1' then
---			row_addr <= std_logic_vector(unsigned(row_addr)+1);
---		elsif ne_hsync='1' then
---			fp_counter <= front_porch;
---			active_counter <=hres;
---			p_clk_div <=p_clk_multiple;
---			addr<=row_addr;
---		elsif fp_counter /= 0 then
---			fp_counter <= fp_counter -1;
---		elsif active_counter /= 0 then	
---			if p_clk_div = 0 then
---				p_clk_div <=p_clk_multiple;
---				active_counter <= active_counter  -1;
---		   		addr <= std_logic_vector(unsigned(addr)+vres);
---			else 
---				p_clk_div <= p_clk_div - 1;
---			end if;
---		else 
---			p_clk_div <=p_clk_multiple;
---		end if;
---	end if;
---	end process;
---			
+--      process (sys_rst_n,p_clk,d_hsync,d_vsync)  begin
+--      if sys_rst_n = '0' then
+--              row_addr<=(others =>'0');
+--              addr<=(others =>'0');
+--              p_clk_div<=p_clk_multiple;
+--              active_counter <=0;
+--              fp_counter <=0;
+--      elsif rising_edge(p_clk) then
+--              if d_vsync='1' then
+--                      row_addr<=(others => '0');
+--                      addr<=(others => '0');
+--                      fp_counter <= front_porch;
+--                      active_counter <=hres;
+--                      p_clk_div <=p_clk_multiple;
+--              elsif pe_gsync ='1' then
+--                      row_addr <= std_logic_vector(unsigned(row_addr)+1);
+--              elsif ne_hsync='1' then
+--                      fp_counter <= front_porch;
+--                      active_counter <=hres;
+--                      p_clk_div <=p_clk_multiple;
+--                      addr<=row_addr;
+--              elsif fp_counter /= 0 then
+--                      fp_counter <= fp_counter -1;
+--              elsif active_counter /= 0 then  
+--                      if p_clk_div = 0 then
+--                              p_clk_div <=p_clk_multiple;
+--                              active_counter <= active_counter  -1;
+--                              addr <= std_logic_vector(unsigned(addr)+vres);
+--                      else 
+--                              p_clk_div <= p_clk_div - 1;
+--                      end if;
+--              else 
+--                      p_clk_div <=p_clk_multiple;
+--              end if;
+--      end if;
+--      end process;
+--                      
 --
 --        wren <= '1' when p_clk_div=2 else '0';
 --
---	addr_out <= addr;
+--      addr_out <= addr;
 --        video_out <= (s_video, s_bright);
 --        wren_out <= wren;
 --
diff --git a/spartan6/hp_lcd_driver/input_stage.vhdl b/spartan6/hp_lcd_driver/input_stage.vhdl
index 7211cf7..077d8a3 100644
--- a/spartan6/hp_lcd_driver/input_stage.vhdl
+++ b/spartan6/hp_lcd_driver/input_stage.vhdl
@@ -1,80 +1,80 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
-ENTITY input_stage IS
+entity input_stage is
     generic (debounce_stages : natural := 2;
              sync_stages     : natural := 2;
-	     video_width     : natural := 2;
-	     addr_width      : natural := 17;
-		clk_multiple : natural := 4; 
-		phase : natural := 2;
-		h_front_porch : natural := 208;
-		h_active : natural := 592;
-		v_front_porch : natural := 2;
-		v_active : natural := 384;
-		h_stride : natural := 384;
-		v_stride : natural := 1);
-	PORT
-	(
-	  clk : in std_logic;
-	  sys_rst_n : in std_logic;
+             video_width     : natural := 2;
+             addr_width      : natural := 17;
+             clk_multiple    : natural := 4;
+             phase           : natural := 2;
+             h_front_porch   : natural := 208;
+             h_active        : natural := 592;
+             v_front_porch   : natural := 2;
+             v_active        : natural := 384;
+             h_stride        : natural := 384;
+             v_stride        : natural := 1);
+    port
+        (
+            clk       : in std_logic;
+            sys_rst_n : in std_logic;
 
-	  video_in:in std_logic_vector(video_width -1 downto 0);
+            video_in : in std_logic_vector(video_width -1 downto 0);
 
-	  hsync_in:in std_logic;
-	  vsync_in: in std_logic;
+            hsync_in : in std_logic;
+            vsync_in : in std_logic;
 
-	  video_out: out std_logic_vector(video_width-1  downto 0);
-	  addr_out : out std_logic_vector(addr_width - 1 downto 0);
-	  wren_out : out std_logic
-	  );
-END input_stage;
+            video_out : out std_logic_vector(video_width-1 downto 0);
+            addr_out  : out std_logic_vector(addr_width - 1 downto 0);
+            wren_out  : out std_logic
+            );
+end input_stage;
 
 
-ARCHITECTURE beh OF input_stage IS
+architecture beh of input_stage is
 
- signal s_hsync: std_logic;
- signal d_hsync: std_logic;
+    signal s_hsync : std_logic;
+    signal d_hsync : std_logic;
 
- signal s_vsync: std_logic;
- signal d_vsync: std_logic;
+    signal s_vsync : std_logic;
+    signal d_vsync : std_logic;
 
- signal s_video: std_logic_vector(video_width-1 downto 0);
+    signal s_video : std_logic_vector(video_width-1 downto 0);
 
- signal addr: std_logic_vector(addr_width - 1 downto 0);
- signal wren : std_logic;
+    signal addr : std_logic_vector(addr_width - 1 downto 0);
+    signal wren : std_logic;
 
 begin
 
-    video_sync_for: for b in 0 to video_width -1 generate
-      sync: entity work.synchronizer
-		generic map(stages => sync_stages + debounce_stages)
-		port map (
-			clk=>clk,
-			i => video_in(b),
-			o =>s_video(b)
-			);
+    video_sync_for : for b in 0 to video_width -1 generate
+        sync : entity work.synchronizer
+            generic map(stages => sync_stages + debounce_stages)
+            port map (
+                clk => clk,
+                i   => video_in(b),
+                o   => s_video(b)
+                );
     end generate;
 
-   video_out <= s_video;
+    video_out <= s_video;
 
 
-    hsync_sync: entity work.synchronizer
-		generic map(stages => sync_stages)
-		port map (
-			clk=>clk,
-			i => hsync_in,
-			o =>s_hsync
-			);
+    hsync_sync : entity work.synchronizer
+        generic map(stages => sync_stages)
+        port map (
+            clk => clk,
+            i   => hsync_in,
+            o   => s_hsync
+            );
 
-    vsync_sync: entity work.synchronizer
-		generic map(stages => sync_stages  )
-		port map (
-			clk=>clk,
-			i => vsync_in,
-			o =>s_vsync
-			);
+    vsync_sync : entity work.synchronizer
+        generic map(stages => sync_stages)
+        port map (
+            clk => clk,
+            i   => vsync_in,
+            o   => s_vsync
+            );
 
     hsync_debounce : entity work.debounce
         generic map(stages => debounce_stages)
@@ -93,29 +93,29 @@ begin
             o   => d_vsync);
 
 
-    input_formatter: entity work.input_formatter
-	generic map(
-		-- 20.000 592 608 680 816 384 385 400 402
-		addr_width => addr_width,
-		clk_multiple => clk_multiple,
-		phase => phase,
-		h_front_porch => h_front_porch,
-		h_active => h_active,
-		v_front_porch => v_front_porch,
-		v_active => v_active,
-		h_stride => h_stride,
-		v_stride => v_stride)
-	port map (
-	  	sys_rst_n => sys_rst_n,
-		clk => clk,
-		hsync => d_hsync,
-		vsync => d_vsync,
-		addr_out => addr,
-		wren_out => wren
-	);
-
-
-	addr_out <= addr;
-	wren_out <= wren;
+    input_formatter : entity work.input_formatter
+        generic map(
+            -- 20.000 592 608 680 816 384 385 400 402
+            addr_width    => addr_width,
+            clk_multiple  => clk_multiple,
+            phase         => phase,
+            h_front_porch => h_front_porch,
+            h_active      => h_active,
+            v_front_porch => v_front_porch,
+            v_active      => v_active,
+            h_stride      => h_stride,
+            v_stride      => v_stride)
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => clk,
+            hsync     => d_hsync,
+            vsync     => d_vsync,
+            addr_out  => addr,
+            wren_out  => wren
+            );
+
+
+    addr_out <= addr;
+    wren_out <= wren;
 
 end beh;
diff --git a/spartan6/hp_lcd_driver/output_analog.vhdl b/spartan6/hp_lcd_driver/output_analog.vhdl
index 30e7d97..35b509f 100644
--- a/spartan6/hp_lcd_driver/output_analog.vhdl
+++ b/spartan6/hp_lcd_driver/output_analog.vhdl
@@ -1,80 +1,82 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
 
-ENTITY output_analog IS
-	PORT
-	(
-	  clk : in std_logic;
-	  sys_rst_n : in std_logic;
+entity output_analog is
+    port
+        (
+            clk       : in std_logic;
+            sys_rst_n : in std_logic;
 
-	  red_in: in std_logic;
-	  green_in: in std_logic;
-	  blue_in: in std_logic;
-	  hsync_in: in std_logic;
-	  vsync_in: in std_logic;
-	  blank_in: in std_logic;
+            red_in   : in std_logic;
+            green_in : in std_logic;
+            blue_in  : in std_logic;
+            hsync_in : in std_logic;
+            vsync_in : in std_logic;
+            blank_in : in std_logic;
 
-	  red_out:out std_logic;
-	  green_out:out std_logic;
-	  blue_out:out std_logic;
-	  hsync_out:out std_logic;
-	  vsync_out:out std_logic
-	  );
-END output_analog;
+            red_out   : out std_logic;
+            green_out : out std_logic;
+            blue_out  : out std_logic;
+            hsync_out : out std_logic;
+            vsync_out : out std_logic
+            );
+end output_analog;
 
 
-ARCHITECTURE beh OF output_analog IS
+architecture beh of output_analog is
 
 
- signal red_r : std_logic;
- signal green_r : std_logic;
- signal blue_r : std_logic;
+    signal red_r   : std_logic;
+    signal green_r : std_logic;
+    signal blue_r  : std_logic;
 
- signal hsync_r : std_logic;
- signal vsync_r : std_logic;
- signal blank_r : std_logic;
+    signal hsync_r : std_logic;
+    signal vsync_r : std_logic;
+    signal blank_r : std_logic;
 
 
 
 begin
 
-process (sys_rst_n,clk) begin
-if sys_rst_n ='0' then
-	red_r<='0';
-	green_r<='0';
-	blue_r<='0';
-	hsync_r<='0';
-	vsync_r<='0';
-	blank_r <= '0';
-elsif rising_edge(clk) then
-	red_r<=red_in;
-	green_r<=green_in;
-	blue_r<=blue_in;
-	hsync_r<=hsync_in;
-	vsync_r<=vsync_in;
-	blank_r <=blank_in;
-
-end if;
-end process;
-
-
-process (sys_rst_n,clk) begin
-if sys_rst_n ='0' then
-	red_out<='0';
-	green_out<='0';
-	blue_out<='0';
-	hsync_out<='0';
-	vsync_out<='0';
-elsif rising_edge(clk) then
-	red_out<=red_r and not blank_r;
-	green_out<=green_r and not blank_r;
-	blue_out<=blue_r and not blank_r;
-	hsync_out<=hsync_r;
-	vsync_out<=vsync_r;
-end if;
-end process;
+    process (sys_rst_n, clk)
+    begin
+        if sys_rst_n = '0' then
+            red_r   <= '0';
+            green_r <= '0';
+            blue_r  <= '0';
+            hsync_r <= '0';
+            vsync_r <= '0';
+            blank_r <= '0';
+        elsif rising_edge(clk) then
+            red_r   <= red_in;
+            green_r <= green_in;
+            blue_r  <= blue_in;
+            hsync_r <= hsync_in;
+            vsync_r <= vsync_in;
+            blank_r <= blank_in;
+
+        end if;
+    end process;
+
+
+    process (sys_rst_n, clk)
+    begin
+        if sys_rst_n = '0' then
+            red_out   <= '0';
+            green_out <= '0';
+            blue_out  <= '0';
+            hsync_out <= '0';
+            vsync_out <= '0';
+        elsif rising_edge(clk) then
+            red_out   <= red_r and not blank_r;
+            green_out <= green_r and not blank_r;
+            blue_out  <= blue_r and not blank_r;
+            hsync_out <= hsync_r;
+            vsync_out <= vsync_r;
+        end if;
+    end process;
 
 
 end beh;
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
index 8eff2de..839fb6d 100644
--- a/spartan6/hp_lcd_driver/output_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -1,52 +1,52 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
 
 
-ENTITY output_formatter IS
-    generic ( addr_width      : natural := 17;
-		h_front_porch : natural := 208;
-		h_active :natural := 384;
-		h_sync_start :natural := 400;
-		h_sync_end :natural := 440;
-		h_total :natural :=600;
-		v_active :natural :=592;
-		v_sync_start:natural:=593;
-		v_sync_end:natural :=596;
-		v_total:natural :=614;
-		h_stride :natural := 1;
-		v_stride :natural := 384
-	);
-	port (
-	  	sys_rst_n : in std_logic;
-		clk : in std_logic;
-		vsync_in : in std_logic;
-		addr_out : out std_logic_vector(addr_width -1 downto 0);
-		blank_out  : out std_logic;
-		vsync_out  : out std_logic;
-		hsync_out  : out std_logic
-	);
-END output_formatter;
+entity output_formatter is
+    generic (addr_width    : natural := 17;
+             h_front_porch : natural := 208;
+             h_active      : natural := 384;
+             h_sync_start  : natural := 400;
+             h_sync_end    : natural := 440;
+             h_total       : natural := 600;
+             v_active      : natural := 592;
+             v_sync_start  : natural := 593;
+             v_sync_end    : natural := 596;
+             v_total       : natural := 614;
+             h_stride      : natural := 1;
+             v_stride      : natural := 384
+             );
+    port (
+        sys_rst_n : in  std_logic;
+        clk       : in  std_logic;
+        vsync_in  : in  std_logic;
+        addr_out  : out std_logic_vector(addr_width -1 downto 0);
+        blank_out : out std_logic;
+        vsync_out : out std_logic;
+        hsync_out : out std_logic
+        );
+end output_formatter;
 
 
-ARCHITECTURE beh OF output_formatter IS
+architecture beh of output_formatter is
 
-   signal row_addr : std_logic_vector(addr_width-1 downto 0)	;
-   signal addr : std_logic_vector(addr_width-1 downto 0)	;
+    signal row_addr : std_logic_vector(addr_width-1 downto 0);
+    signal addr     : std_logic_vector(addr_width-1 downto 0);
 
-   signal vsync_in_ne: std_logic;
+    signal vsync_in_ne : std_logic;
 
-   signal h:natural;
-   signal v:natural;
+    signal h : natural;
+    signal v : natural;
 
 
-   signal blank:std_logic;
-   signal vblank:std_logic;
-   signal vsync:std_logic;
-   signal hsync:std_logic;
+    signal blank  : std_logic;
+    signal vblank : std_logic;
+    signal vsync  : std_logic;
+    signal hsync  : std_logic;
+
 
-		
 begin
 
     vsync_ed : entity work.edge_det
@@ -55,71 +55,73 @@ begin
             sig => vsync_in,
             ne  => vsync_in_ne);
 
-    process (clk, vsync_in_ne,sys_rst_n) begin
-	if sys_rst_n='0' then 
-		h<=0;	
-		v<=0;
-	elsif rising_edge(clk) then
-		if h /= (h_total-1) then
-		  h<=h+1;
-		else 
-		  if v /= (v_total-1) then 
-		    v<=v+1;
-		    h<=0;
-		  elsif vsync_in_ne='1' then
-			h<=0;
-			v<=0;
-		  end if;
-	     end if;
-	end if;
+    process (clk, vsync_in_ne, sys_rst_n)
+    begin
+        if sys_rst_n = '0' then
+            h <=0;
+            v <=0;
+        elsif rising_edge(clk) then
+            if h /= (h_total-1) then
+                h <=h+1;
+            else
+                if v /= (v_total-1) then
+                    v <=v+1;
+                    h <=0;
+                elsif vsync_in_ne = '1' then
+                    h <=0;
+                    v <=0;
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+    process (clk, h, h, sys_rst_n)
+    begin
+        if sys_rst_n = '0' then
+            row_addr <= (others => '0');
+            addr     <= (others => '0');
+            blank    <= '1';
+            vsync    <= '0';
+            hsync    <= '0';
+        elsif rising_edge(clk) then
+
+            if h = 0 then
+                if v = 0 then
+                    row_addr <= (others => '0');
+                    addr     <= (others => '0');
+                    blank    <= '0';
+                    vblank   <= '0';
+                elsif v = v_active then
+                    vblank <= '1';
+                elsif v = v_sync_start then
+                    vsync <= '1';
+                elsif v = v_sync_end then
+                    vsync <= '0';
+                else
+                    blank    <= vblank;
+                    row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
+                    addr     <= row_addr;
+                end if;
+            elsif h = h_active then
+                blank <= '1';
+            elsif h = h_sync_start then
+                hsync <= '1';
+            elsif h = h_sync_end then
+                hsync <= '0';
+            else
+                addr <= std_logic_vector(unsigned(addr)+h_stride);
+            end if;
+        end if;
     end process;
-		
-
-    process (clk,h,h,sys_rst_n) begin
-	if sys_rst_n='0' then 
-		row_addr <=(others =>'0');
-		addr <=(others =>'0');
-		blank <='1';
-		vsync <='0';
-		hsync <='0';
-	elsif rising_edge(clk) then
-
-		if h=0 then
-			if v= 0 then
-				row_addr <=(others =>'0');
-				addr <=(others =>'0');
-				blank<='0';
-				vblank <='0';
-			elsif v=v_active then
-				vblank<='1';
-			elsif v=v_sync_start then
-				vsync<='1';
-			elsif v=v_sync_end then
-				vsync<='0';
-			else
-				blank <=vblank;
-				row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
-				addr <=row_addr;
-			end if;		
-		elsif h=h_active then
-			blank<='1';
-		elsif h=h_sync_start then
-			hsync<='1';
-		elsif h=h_sync_end then
-			hsync<='0';
-		else
-			addr <= std_logic_vector(unsigned(addr)+h_stride);
-		end if;
-	end if;
-      end process;
-			
-
-      addr_out <= addr;
-      blank_out <= blank;
-      hsync_out <= hsync;
-      vsync_out <= vsync;
+
+
+    addr_out  <= addr;
+    blank_out <= blank;
+    hsync_out <= hsync;
+    vsync_out <= vsync;
 
 end beh;
 
 
-	
+
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index 7b977a4..d5cf87a 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -1,79 +1,79 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
-Library UNISIM;
+library UNISIM;
 use UNISIM.vcomponents.all;
 
 
-ENTITY output_stage IS
+entity output_stage is
     generic (debounce_stages : natural := 2;
              sync_stages     : natural := 2;
-	     addr_width      : natural := 17;
-		h_front_porch : natural := 208;
-		h_active :natural := 384;
-		h_sync_start :natural := 400;
-		h_sync_end :natural := 440;
-		h_total :natural:=600;
-		v_active :natural :=592;
-		v_sync_start:natural:=593;
-		v_sync_end:natural :=596;
-		v_total:natural :=614;
-		h_stride :natural := 1;
-		v_stride :natural := 384
-	);
-	PORT
-	(
-	  clk : in std_logic;
-	  sys_rst_n : in std_logic;
+             addr_width      : natural := 17;
+             h_front_porch   : natural := 208;
+             h_active        : natural := 384;
+             h_sync_start    : natural := 400;
+             h_sync_end      : natural := 440;
+             h_total         : natural := 600;
+             v_active        : natural := 592;
+             v_sync_start    : natural := 593;
+             v_sync_end      : natural := 596;
+             v_total         : natural := 614;
+             h_stride        : natural := 1;
+             v_stride        : natural := 384
+             );
+    port
+        (
+            clk       : in std_logic;
+            sys_rst_n : in std_logic;
 
-	  vsync_in: in std_logic;
+            vsync_in : in std_logic;
 
-	  addr_out : out std_logic_vector(addr_width - 1 downto 0);
+            addr_out : out std_logic_vector(addr_width - 1 downto 0);
 
-	  red_in:in std_logic_vector(7 downto 0);
-	  green_in:in std_logic_vector(7 downto 0);
-	  blue_in:in std_logic_vector(7 downto 0);
+            red_in   : in std_logic_vector(7 downto 0);
+            green_in : in std_logic_vector(7 downto 0);
+            blue_in  : in std_logic_vector(7 downto 0);
 
 
-	  red_out:out std_logic;
-	  green_out:out std_logic;
-	  blue_out:out std_logic;
-	  hsync_out:out std_logic;
-	  vsync_out:out std_logic;
-	  
-	  hdmi_c: out std_logic;
-	  hdmi_r: out std_logic;
-	  hdmi_g: out std_logic;
-	  hdmi_b: out std_logic
-	  );
-END output_stage;
+            red_out   : out std_logic;
+            green_out : out std_logic;
+            blue_out  : out std_logic;
+            hsync_out : out std_logic;
+            vsync_out : out std_logic;
 
+            hdmi_c : out std_logic;
+            hdmi_r : out std_logic;
+            hdmi_g : out std_logic;
+            hdmi_b : out std_logic
+            );
+end output_stage;
 
-ARCHITECTURE beh OF output_stage IS
 
- signal n_clk : std_logic;
+architecture beh of output_stage is
 
- signal s_vsync_in: std_logic;
- signal d_vsync_in: std_logic;
+    signal n_clk : std_logic;
 
- signal blank: std_logic;
+    signal s_vsync_in : std_logic;
+    signal d_vsync_in : std_logic;
 
- signal hsync: std_logic;
- signal vsync: std_logic;
+    signal blank : std_logic;
 
- signal addr: std_logic_vector(addr_width - 1 downto 0);
+    signal hsync : std_logic;
+    signal vsync : std_logic;
 
- begin
+    signal addr : std_logic_vector(addr_width - 1 downto 0);
 
+begin
 
-    vsync_sync: entity work.synchronizer
-		generic map(stages => sync_stages  )
-		port map (
-			clk=>clk,
-			i => vsync_in,
-			o =>s_vsync_in
-			);
+
+    vsync_sync : entity work.synchronizer
+        generic map(stages => sync_stages)
+        port map (
+            clk => clk,
+            i   => vsync_in,
+            o   => s_vsync_in
+            );
 
     vsync_debounce : entity work.debounce
         generic map(stages => debounce_stages)
@@ -83,71 +83,71 @@ ARCHITECTURE beh OF output_stage IS
             o   => d_vsync_in);
 
 
-    output_formatter: entity work.output_formatter
-	generic map(
-		addr_width => addr_width,
-		h_active  => h_active,
-		h_sync_start  => h_sync_start,
-		h_sync_end  => h_sync_end,
-		h_total  => h_total,
-		v_active => v_active,
-		v_sync_start => v_sync_start,
-		v_sync_end => v_sync_end,
-		v_total => v_total,
-		h_stride  => h_stride,
-		v_stride  => v_stride)
-	port map (
-	  	sys_rst_n => sys_rst_n,
-		clk => clk,
-		vsync_in => d_vsync_in,
-		addr_out => addr,
-		blank_out => blank,
-		vsync_out => vsync,
-		hsync_out => hsync
-	);
-
-
-	addr_out <= addr;
+    output_formatter : entity work.output_formatter
+        generic map(
+            addr_width   => addr_width,
+            h_active     => h_active,
+            h_sync_start => h_sync_start,
+            h_sync_end   => h_sync_end,
+            h_total      => h_total,
+            v_active     => v_active,
+            v_sync_start => v_sync_start,
+            v_sync_end   => v_sync_end,
+            v_total      => v_total,
+            h_stride     => h_stride,
+            v_stride     => v_stride)
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => clk,
+            vsync_in  => d_vsync_in,
+            addr_out  => addr,
+            blank_out => blank,
+            vsync_out => vsync,
+            hsync_out => hsync
+            );
+
+
+    addr_out <= addr;
 
 
     output_analog : entity work.output_analog
-	port map(
-	  	sys_rst_n => sys_rst_n,
-		clk => clk,
+        port map(
+            sys_rst_n => sys_rst_n,
+            clk       => clk,
 
-		hsync_in => hsync,
-		vsync_in => vsync,
-		blank_in => blank,
-		red_in => green_in(7),
-		green_in => green_in(6),
-		blue_in => blue_in(7),
+            hsync_in => hsync,
+            vsync_in => vsync,
+            blank_in => blank,
+            red_in   => green_in(7),
+            green_in => green_in(6),
+            blue_in  => blue_in(7),
 
-		red_out => red_out,
-		green_out => green_out,
-		blue_out => blue_out,
-		hsync_out =>  hsync_out,
-		vsync_out => vsync_out
-	);
+            red_out   => red_out,
+            green_out => green_out,
+            blue_out  => blue_out,
+            hsync_out => hsync_out,
+            vsync_out => vsync_out
+            );
 
 
 
 
-n_clk <= not clk;
-hdmi_r <= hsync;
-hdmi_g <= vsync;
-hdmi_b <= green_in(7);
+    n_clk  <= not clk;
+    hdmi_r <= hsync;
+    hdmi_g <= vsync;
+    hdmi_b <= green_in(7);
 
 
 
-o_clk_buf: ODDR2
-port map (
-   D0 => '1',
-   D1 => '0',
-   C0 => clk,
-   C1 => n_clk,
-   CE =>'1',
-   Q => hdmi_c
-);
+    o_clk_buf : ODDR2
+        port map (
+            D0 => '1',
+            D1 => '0',
+            C0 => clk,
+            C1 => n_clk,
+            CE => '1',
+            Q  => hdmi_c
+            );
 
 
 end beh;
diff --git a/spartan6/hp_lcd_driver/synchronizer.vhdl b/spartan6/hp_lcd_driver/synchronizer.vhdl
index 99618b9..302cef9 100644
--- a/spartan6/hp_lcd_driver/synchronizer.vhdl
+++ b/spartan6/hp_lcd_driver/synchronizer.vhdl
@@ -16,7 +16,7 @@ begin
 
     o <= flipflops(flipflops'high);
 
-    clk_proc : process(clk,flipflops,i)
+    clk_proc : process(clk, flipflops, i)
     begin
         if rising_edge(clk) then
             flipflops <= flipflops(flipflops'high-1 downto 0) & i;