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| author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-16 19:03:20 +0100 |
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| committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-16 19:03:20 +0100 |
| commit | d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7 (patch) | |
| tree | 7cb2803defad3066ae308c357d1e2dba1db6e577 /pll32.qip | |
| parent | 3975fdfe4275347dab666e43dbfdaebe80c58ff8 (diff) | |
| download | fpga-bbc-d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7.tar.gz fpga-bbc-d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7.tar.bz2 fpga-bbc-d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7.zip | |
Added top-level, PLL, MOS ROM and CRTC. CRTC seems to behave strangely although the design is passing timing.
Diffstat (limited to 'pll32.qip')
| -rw-r--r-- | pll32.qip | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/pll32.qip b/pll32.qip new file mode 100644 index 0000000..f78bd93 --- /dev/null +++ b/pll32.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll32.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll32.ppf"]
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