From d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7 Mon Sep 17 00:00:00 2001
From: Mike Stirling <opensource@mikestirling.co.uk>
Date: Sat, 16 Jul 2011 19:03:20 +0100
Subject: Added top-level, PLL, MOS ROM and CRTC.  CRTC seems to behave
 strangely although the design is passing timing.

---
 pll32.qip | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 pll32.qip

(limited to 'pll32.qip')

diff --git a/pll32.qip b/pll32.qip
new file mode 100644
index 0000000..f78bd93
--- /dev/null
+++ b/pll32.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll32.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll32.ppf"]
-- 
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