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| author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-16 19:03:20 +0100 |
|---|---|---|
| committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-16 19:03:20 +0100 |
| commit | d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7 (patch) | |
| tree | 7cb2803defad3066ae308c357d1e2dba1db6e577 /pll32.ppf | |
| parent | 3975fdfe4275347dab666e43dbfdaebe80c58ff8 (diff) | |
| download | fpga-bbc-d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7.tar.gz fpga-bbc-d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7.tar.bz2 fpga-bbc-d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7.zip | |
Added top-level, PLL, MOS ROM and CRTC. CRTC seems to behave strangely although the design is passing timing.
Diffstat (limited to 'pll32.ppf')
| -rw-r--r-- | pll32.ppf | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/pll32.ppf b/pll32.ppf new file mode 100644 index 0000000..1ba6b2c --- /dev/null +++ b/pll32.ppf @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll32" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external" />
+<pin name="inclk0" direction="input" scope="external" source="clock" />
+<pin name="c0" direction="output" scope="external" source="clock" />
+<pin name="locked" direction="output" scope="external" />
+
+</global>
+</pinplan>
|