From d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7 Mon Sep 17 00:00:00 2001
From: Mike Stirling <opensource@mikestirling.co.uk>
Date: Sat, 16 Jul 2011 19:03:20 +0100
Subject: Added top-level, PLL, MOS ROM and CRTC.  CRTC seems to behave
 strangely although the design is passing timing.

---
 pll32.ppf | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 pll32.ppf

(limited to 'pll32.ppf')

diff --git a/pll32.ppf b/pll32.ppf
new file mode 100644
index 0000000..1ba6b2c
--- /dev/null
+++ b/pll32.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll32" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
-- 
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