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author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-30 10:39:52 +0100 |
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committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-30 10:39:52 +0100 |
commit | fc9ea65b8ac1849c9756cc58e6f14500646b1d8c (patch) | |
tree | 7a520dc724130cda33537f79b01fe3129f6bd9c0 /m6522_tb.vhd | |
parent | 22139faee8f39c1a2d5e03f35d586fcf3eda472b (diff) | |
download | fpga-bbc-fc9ea65b8ac1849c9756cc58e6f14500646b1d8c.tar.gz fpga-bbc-fc9ea65b8ac1849c9756cc58e6f14500646b1d8c.tar.bz2 fpga-bbc-fc9ea65b8ac1849c9756cc58e6f14500646b1d8c.zip |
Keyboard now working (needed to loop back slow bus outputs to inputs on system VIA). Added aux input to debugger for display of arbitrary hex values. Removed test IFR output from 6522
Diffstat (limited to 'm6522_tb.vhd')
-rw-r--r-- | m6522_tb.vhd | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/m6522_tb.vhd b/m6522_tb.vhd index eb76db5..023eb2e 100644 --- a/m6522_tb.vhd +++ b/m6522_tb.vhd @@ -46,8 +46,7 @@ component M6522 is I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
- CLK : in std_logic;
- testout : out std_logic_vector(7 downto 0)
+ CLK : in std_logic
);
end component;
@@ -81,8 +80,6 @@ signal n_reset : std_logic := '0'; signal clken : std_logic := '0';
signal clock : std_logic := '0';
-signal testout : std_logic_vector(7 downto 0);
-
begin
uut: m6522 port map (
@@ -93,7 +90,7 @@ begin cb1_in, cb1_out, n_cb1_oe,
cb2_in, cb2_out, n_cb2_oe,
pb_in, pb_out, n_pb_oe,
- phase2, n_reset, clken, clock, testout
+ phase2, n_reset, clken, clock
);
clock <= not clock after 125 ns; -- 4x 1 MHz
|