Added pin definitions for SD card interface. Fixed bug in 6522 shift-register implementation (shift on CB1 rising edge should occur even in SR disabled mode). Works with MMBEEB SD card interface ROM.

4 files changed, 50 insertions, 27 deletions

diff --git a/CII_Starter_pin_assignments.csv b/CII_Starter_pin_assignments.csv
index c63a6de..f46adb0 100644
--- a/CII_Starter_pin_assignments.csv
+++ b/CII_Starter_pin_assignments.csv
@@ -448,3 +448,8 @@ From,To,Assignment Name,Value,Enabled
 ,SRAM_OE_N,Location,PIN_T8,Yes

 ,SRAM_UB_N,Location,PIN_W7,Yes

 ,SRAM_WE_N,Location,PIN_AA10,Yes

+,SD_nCS,Location,PIN_U20,Yes

+,SD_MOSI,Location,PIN_Y20,Yes

+,SD_SCLK,Location,PIN_V20,Yes

+,SD_MISO,Location,PIN_W20,Yes

+

diff --git a/bbc_micro_de1.qsf b/bbc_micro_de1.qsf
index 99dc850..1ecc8b9 100644
--- a/bbc_micro_de1.qsf
+++ b/bbc_micro_de1.qsf
@@ -519,4 +519,12 @@ set_global_assignment -name QIP_FILE ehbasic.qip
 set_global_assignment -name VHDL_FILE m6522_tb.vhd

 set_global_assignment -name VHDL_FILE keyboard.vhd

 set_global_assignment -name VHDL_FILE debugger.vhd

+set_global_assignment -name USE_CONFIGURATION_DEVICE ON

+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4

+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"

+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

+set_location_assignment PIN_U20 -to SD_nCS

+set_location_assignment PIN_V20 -to SD_SCLK

+set_location_assignment PIN_Y20 -to SD_MOSI

+set_location_assignment PIN_W20 -to SD_MISO

 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd
index a32d934..77922e2 100644
--- a/bbc_micro_de1.vhd
+++ b/bbc_micro_de1.vhd
@@ -90,6 +90,12 @@ port (
 	FL_WE_N		:	out		std_logic;

 	FL_CE_N		:	out		std_logic;

 	

+	-- SD card (SPI mode)

+	SD_nCS		:	out		std_logic;

+	SD_MOSI		:	out		std_logic;

+	SD_SCLK		:	out		std_logic;

+	SD_MISO		:	in		std_logic;

+	

 	-- GPIO

 	GPIO_0		:	inout	std_logic_vector(35 downto 0);

 	GPIO_1		:	inout	std_logic_vector(35 downto 0)

@@ -912,7 +918,7 @@ begin
 		"00" when mos_enable = '1' else

 		"01" when rom_enable = '1' and romsel(1 downto 0) = "11" else	-- BASIC

 		"10" when rom_enable = '1' and romsel(1 downto 0) = "00" else	-- DFS

-		"11";

+		"11"; -- MMC ROM

 		

 	-- SRAM bus

 	SRAM_UB_N <= '1';

@@ -1017,7 +1023,15 @@ begin
 	

 	-- Connections to User VIA (user port is output on green LEDs)

 	user_via_ca1_in <= '1'; -- Pulled up

-	LEDG <= user_via_pb_out;

+	--LEDG <= user_via_pb_out;

+	

+	-- MMBEEB

+	user_via_cb1_in <= user_via_pb_out(1);

+	SD_SCLK <= user_via_pb_out(1); -- SCLK

+	SD_MOSI <= user_via_pb_out(0); -- SDO

+	SD_nCS <= '0'; -- CS

+	user_via_cb2_in <= SD_MISO; -- SDI

+	user_via_pb_in <= user_via_pb_out;

 	

 	-- ROM select latch

 	process(clock,reset_n)

@@ -1060,8 +1074,8 @@ begin
 	-- DEBUG STUFF

 	-----------------

 	

-	GPIO_0(0) <= cpu_irq_n;

-	GPIO_0(1) <= keyb_out;

-	GPIO_0(2) <= keyb_enable_n;

+	GPIO_0(0) <= user_via_pb_out(1); --clk

+	GPIO_0(1) <= user_via_pb_out(0); --do

+	GPIO_0(2) <= SD_MISO; -- di

 

 end architecture;

diff --git a/m6522.vhd b/m6522.vhd
index fe82b3f..7cd026c 100644
--- a/m6522.vhd
+++ b/m6522.vhd
@@ -733,7 +733,7 @@ begin
         free_run := '0';

 

         case r_acr(4 downto 2) is

-          when "000" => ena := '0';

+          when "000" => ena := '0'; cb1_ip := '1';

           when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';

           when "010" => ena := '1'; cb1_op := '1';

           when "011" => ena := '1'; cb1_ip := '1';

@@ -745,35 +745,31 @@ begin
         end case;

 

         -- clock select

-        if (ena = '0') then

-          sr_strobe <= '1';

-        else

-          if (cb1_ip = '1') then

-            sr_strobe <= I_CB1;

-          else

-            if (sr_cnt(3) = '0') and (free_run = '0') then

-              sr_strobe <= '1';

-            else

-              if ((use_t2 = '1') and t2_sr_ena) or

-                 ((use_t2 = '0') and (phase = "00")) then

-                  sr_strobe <= not sr_strobe;

-              end if;

-            end if;

-          end if;

-        end if;

+        -- SR still runs even in disabled mode (on rising edge of CB1).  It

+        -- just doesn't generate any interrupts.

+        -- Ref BBC micro advanced user guide p409

+		if (cb1_ip = '1') then

+		  sr_strobe <= I_CB1;

+		else

+		  if (sr_cnt(3) = '0') and (free_run = '0') then

+		    sr_strobe <= '1';

+		  else

+			if ((use_t2 = '1') and t2_sr_ena) or

+			  ((use_t2 = '0') and (phase = "00")) then

+			    sr_strobe <= not sr_strobe;

+			end if;

+		  end if;

+		end if;

 

         -- latch on rising edge, shift on falling edge

         if sr_write_ena then

           r_sr <= load_data;

-        elsif (ena = '1') then -- use shift reg

-

+        else

           if (dir_out = '0') then

             -- input

             if (sr_cnt(3) = '1') or (cb1_ip = '1') then

               if sr_strobe_rising then

-                r_sr(0) <= I_CB2;

-              elsif sr_strobe_falling then

-                r_sr(7 downto 1) <= r_sr(6 downto 0);

+                r_sr <= r_sr(6 downto 0) & I_CB2;

               end if;

             end if;

             sr_out <= '1';