diff options
Diffstat (limited to 'boards/base/STM32F746-Discovery')
9 files changed, 153 insertions, 153 deletions
diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index 575638d5..a3b02ca7 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -461,7 +461,7 @@ static GFXINLINE void post_init_board(GDisplay* g) { (void) g; } -static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent) { +static GFXINLINE void set_backlight(GDisplay* g, gU8 percent) { (void) g; // ST was stupid enought not to hook this up to a pin that diff --git a/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h index 5668e8c4..a1a47a70 100644 --- a/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h +++ b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h @@ -202,39 +202,39 @@ /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((gU16)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((gU16)0x01U) /*!< Transceiver Basic Status Register */ -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ +#define PHY_RESET ((gU16)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((gU16)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((gU16)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((gU16)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((gU16)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((gU16)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((gU16)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((gU16)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((gU16)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((gU16)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((gU16)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((gU16)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((gU16)0x0002U) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ +#define PHY_SR ((gU16)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((gU16)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((gU16)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ -#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ +#define PHY_LINK_STATUS ((gU16)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((gU16)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((gU16)0x0004U) /*!< PHY Duplex mask */ -#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ +#define PHY_MICR_INT_EN ((gU16)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((gU16)0x0001U) /*!< PHY Enable output interrupt events */ -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ +#define PHY_MISR_LINK_INT_EN ((gU16)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((gU16)0x2000U) /*!< PHY link status interrupt mask */ /* ################## SPI peripheral configuration ########################## */ @@ -436,9 +436,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((gU8 *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(gU8* file, gU32 line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ diff --git a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h index bedea770..94c2d2e4 100644 --- a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h +++ b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h @@ -100,11 +100,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((gU32)25000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((gU32)100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -113,14 +113,14 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((gU32)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ + #define LSI_VALUE ((gU32)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -128,11 +128,11 @@ * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE ((gU32)32768U) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT ((gU32)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** @@ -141,7 +141,7 @@ * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ + #define EXTERNAL_CLOCK_VALUE ((gU32)12288000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -151,8 +151,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define VDD_VALUE ((gU32)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((gU32)0x0F) /*!< tick interrupt priority */ #define USE_RTOS 0 #define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */ @@ -178,50 +178,50 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_RXBUFNB ((gU32)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((gU32)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ /* LAN8742A PHY Address*/ #define LAN8742A_PHY_ADDRESS 0x00U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x00000FFFU) +#define PHY_RESET_DELAY ((gU32)0x00000FFFU) /* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) +#define PHY_CONFIG_DELAY ((gU32)0x00000FFFU) -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) +#define PHY_READ_TO ((gU32)0x0000FFFFU) +#define PHY_WRITE_TO ((gU32)0x0000FFFFU) /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((gU16)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((gU16)0x01U) /*!< Transceiver Basic Status Register */ -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ +#define PHY_RESET ((gU16)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((gU16)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((gU16)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((gU16)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((gU16)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((gU16)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((gU16)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((gU16)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((gU16)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((gU16)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((gU16)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((gU16)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((gU16)0x0002U) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */ +#define PHY_SR ((gU16)0x1FU) /*!< PHY special control/ status register Offset */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS ((gU16)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((gU16)0x0010U) /*!< PHY Duplex mask */ -#define PHY_ISFR ((uint16_t)0x1DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */ +#define PHY_ISFR ((gU16)0x1DU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR_INT4 ((gU16)0x0010U) /*!< PHY Link down inturrupt */ /* ################## SPI peripheral configuration ########################## */ @@ -407,9 +407,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((gU8 *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(gU8* file, gU32 line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ diff --git a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h index 2482108d..99b8a852 100644 --- a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h +++ b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h @@ -40,14 +40,14 @@ static gBool init_board(GMouse* m, unsigned instance) GPIOH->MODER |= GPIO_MODER_MODER7_1; // Alternate function GPIOH->OTYPER |= GPIO_OTYPER_OT_7; // OpenDrain GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR7; // LowSpeed - GPIOH->AFRL |= ((uint32_t)0x04 << 4*7); // AF4 + GPIOH->AFRL |= ((gU32)0x04 << 4*7); // AF4 // I2C3_SDA GPIOH8, alternate, opendrain, highspeed RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN; // Enable clock GPIOH->MODER |= GPIO_MODER_MODER8_1; // Alternate function GPIOH->OTYPER |= GPIO_OTYPER_OT_8; // OpenDrain GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR8; // LowSpeed - GPIOH->AFRH |= ((uint32_t)0x04 << 4*0); // AF4 + GPIOH->AFRH |= ((gU32)0x04 << 4*0); // AF4 // Initialize the I2C3 peripheral if (!(i2cInit(I2C3))) { @@ -57,21 +57,21 @@ static gBool init_board(GMouse* m, unsigned instance) return gTrue; } -static void write_reg(GMouse* m, uint8_t reg, uint8_t val) +static void write_reg(GMouse* m, gU8 reg, gU8 val) { (void)m; i2cWriteReg(I2C3, FT5336_SLAVE_ADDR, reg, val); } -static uint8_t read_byte(GMouse* m, uint8_t reg) +static gU8 read_byte(GMouse* m, gU8 reg) { (void)m; return i2cReadByte(I2C3, FT5336_SLAVE_ADDR, reg); } -static uint16_t read_word(GMouse* m, uint8_t reg) +static gU16 read_word(GMouse* m, gU8 reg) { (void)m; diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c index 35a60a97..e90d6793 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -16,8 +16,8 @@ #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 -#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) +#define REFRESH_COUNT ((gU32)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ +#define SDRAM_TIMEOUT ((gU32)0xFFFF) /* DMA definitions for SDRAM DMA transfer */ #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE @@ -26,25 +26,25 @@ #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn /* FMC SDRAM Mode definition register defines */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount); +#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200) + +static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, gU32 RefreshCount); static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); -static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); -static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); -static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); +static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, gU32 Bank); +static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout); +static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, gU32 RefreshRate); static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) { @@ -73,8 +73,8 @@ static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) { - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; + gU32 tmpr1 = 0; + gU32 tmpr2 = 0; /* Set SDRAM bank configuration parameters */ if (Init->SDBank != FMC_SDRAM_BANK2) @@ -82,11 +82,11 @@ static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_In tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + tmpr1 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + tmpr1 |= (gU32)(Init->ColumnBitsNumber |\ Init->RowBitsNumber |\ Init->MemoryDataWidth |\ Init->InternalBankNumber |\ @@ -103,22 +103,22 @@ static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_In tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + tmpr1 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + tmpr1 |= (gU32)(Init->SDClockPeriod |\ Init->ReadBurst |\ Init->ReadPipeDelay); tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + tmpr2 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + tmpr2 |= (gU32)(Init->ColumnBitsNumber |\ Init->RowBitsNumber |\ Init->MemoryDataWidth |\ Init->InternalBankNumber |\ @@ -132,10 +132,10 @@ static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_In return HAL_OK; } -static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, gU32 Bank) { - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; + gU32 tmpr1 = 0; + gU32 tmpr2 = 0; /* Set SDRAM device timing parameters */ if (Bank != FMC_SDRAM_BANK2) @@ -143,11 +143,11 @@ static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_S tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + tmpr1 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ FMC_SDTR1_TRCD)); - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + tmpr1 |= (gU32)(((Timing->LoadToActiveDelay)-1) |\ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ (((Timing->SelfRefreshTime)-1) << 8) |\ (((Timing->RowCycleDelay)-1) << 12) |\ @@ -161,11 +161,11 @@ static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_S tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + tmpr1 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ FMC_SDTR1_TRCD)); - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + tmpr1 |= (gU32)(((Timing->LoadToActiveDelay)-1) |\ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ (((Timing->SelfRefreshTime)-1) << 8) |\ (((Timing->WriteRecoveryTime)-1) <<16) |\ @@ -174,10 +174,10 @@ static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_S tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + tmpr2 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ FMC_SDTR1_TRCD)); - tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + tmpr2 |= (gU32)((((Timing->RowCycleDelay)-1) << 12) |\ (((Timing->RPDelay)-1) << 20)); Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; @@ -229,7 +229,7 @@ void BSP_SDRAM_Init(void) BSP_SDRAM_Initialization_sequence(&sdramHandle, REFRESH_COUNT); } -static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout) { /* Check the SDRAM controller state */ if(hsdram->State == HAL_SDRAM_STATE_BUSY) @@ -256,13 +256,13 @@ static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC return HAL_OK; } -static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout) { - __IO uint32_t tmpr = 0; + __IO gU32 tmpr = 0; gTicks tickstart = 0; /* Set command register */ - tmpr = (uint32_t)((Command->CommandMode) |\ + tmpr = (gU32)((Command->CommandMode) |\ (Command->CommandTarget) |\ (((Command->AutoRefreshNumber)-1) << 5) |\ ((Command->ModeRegisterDefinition) << 9) @@ -291,7 +291,7 @@ static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_S return HAL_OK; } -static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, gU32 RefreshRate) { /* Check the SDRAM controller state */ if(hsdram->State == HAL_SDRAM_STATE_BUSY) @@ -311,7 +311,7 @@ static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdr return HAL_OK; } -static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, gU32 RefreshRate) { /* Set the refresh rate in command register */ Device->SDRTR |= (RefreshRate<<1); @@ -321,7 +321,7 @@ static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + gU32 tmp = 0; /* Check the DMA peripheral state */ if(hdma == NULL) @@ -336,7 +336,7 @@ static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma) tmp = hdma->Instance->CR; /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ - tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + tmp &= ((gU32)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); @@ -361,7 +361,7 @@ static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma) tmp = hdma->Instance->FCR; /* Clear Direct mode and FIFO threshold bits */ - tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + tmp &= (gU32)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; @@ -424,7 +424,7 @@ static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->Instance->M1AR = 0; /* Reset DMA Streamx FIFO control register */ - hdma->Instance->FCR = (uint32_t)0x00000021; + hdma->Instance->FCR = (gU32)0x00000021; /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); @@ -450,7 +450,7 @@ static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @param RefreshCount: SDRAM refresh counter value * @retval None */ -static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount) +static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, gU32 RefreshCount) { FMC_SDRAM_CommandTypeDef Command; @@ -489,7 +489,7 @@ static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint3 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; Command.AutoRefreshNumber = 1; - Command.ModeRegisterDefinition = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + Command.ModeRegisterDefinition = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\ SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ SDRAM_MODEREG_CAS_LATENCY_2 |\ SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h index abf88291..42c49978 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h @@ -44,8 +44,8 @@ extern "C" { #endif -#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) -#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ +#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000) +#define SDRAM_DEVICE_SIZE ((gU32)0x800000) /* SDRAM device size in MBytes */ void BSP_SDRAM_Init(void); diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c index 56d3b16a..e0be3b23 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c @@ -66,11 +66,11 @@ #include "stm32f7xx.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ + #define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -125,9 +125,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 16000000; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + gU32 SystemCoreClock = 16000000; + const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -163,19 +163,19 @@ void SystemInit(void) #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; + RCC->CR |= (gU32)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + RCC->CR &= (gU32)0xFEF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (gU32)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; @@ -230,7 +230,7 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -287,8 +287,8 @@ void SystemCoreClockUpdate(void) */ void SystemInit_ExtMemCtl(void) { - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; + register gU32 tmpreg = 0, timeout = 0xFFFF; + register __IO gU32 index; /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface clock */ diff --git a/boards/base/STM32F746-Discovery/stm32f7_i2c.c b/boards/base/STM32F746-Discovery/stm32f7_i2c.c index 75af9de7..00ad5111 100644 --- a/boards/base/STM32F746-Discovery/stm32f7_i2c.c +++ b/boards/base/STM32F746-Discovery/stm32f7_i2c.c @@ -9,18 +9,18 @@ /* * The CR2 register needs atomic access. Hence always use this function to setup a transfer configuration. */ -static void _i2cConfigTransfer(I2C_TypeDef* i2c, uint16_t slaveAddr, uint8_t numBytes, uint32_t mode, uint32_t request) +static void _i2cConfigTransfer(I2C_TypeDef* i2c, gU16 slaveAddr, gU8 numBytes, gU32 mode, gU32 request) { - uint32_t tmpreg = 0; + gU32 tmpreg = 0; // Get the current CR2 register value tmpreg = i2c->CR2; // Clear tmpreg specific bits - tmpreg &= (uint32_t) ~((uint32_t) (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + tmpreg &= (gU32) ~((gU32) (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); // update tmpreg - tmpreg |= (uint32_t) (((uint32_t) slaveAddr & I2C_CR2_SADD) | (((uint32_t) numBytes << 16) & I2C_CR2_NBYTES) | (uint32_t) mode | (uint32_t) request); + tmpreg |= (gU32) (((gU32) slaveAddr & I2C_CR2_SADD) | (((gU32) numBytes << 16) & I2C_CR2_NBYTES) | (gU32) mode | (gU32) request); // Update the actual CR2 contents i2c->CR2 = tmpreg; @@ -31,7 +31,7 @@ static void _i2cConfigTransfer(I2C_TypeDef* i2c, uint16_t slaveAddr, uint8_t num */ static void _i2cResetCr2(I2C_TypeDef* i2c) { - i2c->CR2 &= (uint32_t) ~((uint32_t) (I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)); + i2c->CR2 &= (gU32) ~((gU32) (I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)); } gBool i2cInit(I2C_TypeDef* i2c) @@ -79,7 +79,7 @@ gBool i2cInit(I2C_TypeDef* i2c) return gTrue; } -void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length) +void i2cSend(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length) { // We are currently not able to send more than 255 bytes at once if (length > 255) { @@ -109,21 +109,21 @@ void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length _i2cResetCr2(i2c); } -void i2cSendByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t data) +void i2cSendByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 data) { i2cSend(i2c, slaveAddr, &data, 1); } -void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t value) +void i2cWriteReg(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr, gU8 value) { - uint8_t txbuf[2]; + gU8 txbuf[2]; txbuf[0] = regAddr; txbuf[1] = value; i2cSend(i2c, slaveAddr, txbuf, 2); } -void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length) +void i2cRead(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length) { int i; @@ -151,9 +151,9 @@ void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length _i2cResetCr2(i2c); } -uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr) +gU8 i2cReadByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr) { - uint8_t ret = 0xAA; + gU8 ret = 0xAA; i2cSend(i2c, slaveAddr, ®Addr, 1); i2cRead(i2c, slaveAddr, &ret, 1); @@ -161,12 +161,12 @@ uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr) return ret; } -uint16_t i2cReadWord(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr) +gU16 i2cReadWord(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr) { - uint8_t ret[2] = { 0xAA, 0xAA }; + gU8 ret[2] = { 0xAA, 0xAA }; i2cSend(i2c, slaveAddr, ®Addr, 1); i2cRead(i2c, slaveAddr, ret, 2); - return (uint16_t)((ret[0] << 8) | (ret[1] & 0x00FF)); + return (gU16)((ret[0] << 8) | (ret[1] & 0x00FF)); } diff --git a/boards/base/STM32F746-Discovery/stm32f7_i2c.h b/boards/base/STM32F746-Discovery/stm32f7_i2c.h index 4d481903..bae4560f 100644 --- a/boards/base/STM32F746-Discovery/stm32f7_i2c.h +++ b/boards/base/STM32F746-Discovery/stm32f7_i2c.h @@ -5,10 +5,10 @@ gBool i2cInit(I2C_TypeDef* i2c); -void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length); -void i2cSendByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t data); -void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t value); +void i2cSend(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length); +void i2cSendByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 data); +void i2cWriteReg(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr, gU8 value); -void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length); -uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr); -uint16_t i2cReadWord(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr); +void i2cRead(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length); +gU8 i2cReadByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr); +gU16 i2cReadWord(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr); |