diff options
Diffstat (limited to 'boards/base/STM32F439i-Eval/CubeHal')
5 files changed, 53 insertions, 53 deletions
diff --git a/boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h b/boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h index 6c2daff8..d598efac 100644 --- a/boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h +++ b/boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h @@ -153,7 +153,7 @@ static GFXINLINE void post_init_board(GDisplay* g) (void) g; } -static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent) +static GFXINLINE void set_backlight(GDisplay* g, gU8 percent) { (void) g; (void) percent; diff --git a/boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h b/boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h index b5221244..380ac0ed 100644 --- a/boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h +++ b/boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h @@ -82,12 +82,12 @@ static gBool init_board(GMouse* m, unsigned driverinstance) return gTrue; } -static gBool read_bytes(GMouse* m, uint8_t reg, uint8_t* buffer, uint8_t nbrBytes) +static gBool read_bytes(GMouse* m, gU8 reg, gU8* buffer, gU8 nbrBytes) { (void)m; - HAL_I2C_Master_Transmit(&_i2cHandle, (uint16_t)EXC7200_SLAVE_ADDR, (uint8_t*)®, 1, 10000); - HAL_I2C_Master_Receive(&_i2cHandle, (uint16_t)EXC7200_SLAVE_ADDR, buffer, nbrBytes, 10000); + HAL_I2C_Master_Transmit(&_i2cHandle, (gU16)EXC7200_SLAVE_ADDR, (gU8*)®, 1, 10000); + HAL_I2C_Master_Receive(&_i2cHandle, (gU16)EXC7200_SLAVE_ADDR, buffer, nbrBytes, 10000); return gTrue; } diff --git a/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c b/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c index 65b78a76..b2cbda39 100644 --- a/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c +++ b/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c @@ -144,9 +144,9 @@ static void SDRAM_MspInit(void); * @brief Initializes the SDRAM device. * @retval SDRAM status */ -uint8_t BSP_SDRAM_Init(void) +gU8 BSP_SDRAM_Init(void) { - static uint8_t sdramstatus = SDRAM_ERROR; + static gU8 sdramstatus = SDRAM_ERROR; /* SDRAM device configuration */ sdramHandle.Instance = FMC_SDRAM_DEVICE; @@ -191,9 +191,9 @@ uint8_t BSP_SDRAM_Init(void) * @brief Programs the SDRAM device. * @param RefreshCount: SDRAM refresh counter value */ -void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount) { - __IO uint32_t tmpmrd = 0; + __IO gU32 tmpmrd = 0; /* Step 1: Configure a clock configuration enable command */ Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; @@ -227,7 +227,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); /* Step 5: Program the external memory mode register */ - tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\ SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ SDRAM_MODEREG_CAS_LATENCY_3 |\ SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ @@ -253,9 +253,9 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) * @param uwDataSize: Size of read data from the memory * @retval SDRAM status */ -uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize) { - if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -272,9 +272,9 @@ uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uw * @param uwDataSize: Size of read data from the memory * @retval SDRAM status */ -uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize) { - if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -291,9 +291,9 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_ * @param uwDataSize: Size of written data from the memory * @retval SDRAM status */ -uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize) { - if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -310,9 +310,9 @@ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t u * @param uwDataSize: Size of written data from the memory * @retval SDRAM status */ -uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize) { - if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -327,7 +327,7 @@ uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32 * @param SdramCmd: Pointer to SDRAM command structure * @retval HAL status */ -uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) +gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) { if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) { diff --git a/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h b/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h index 0f572a03..09d5c3ac 100644 --- a/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h +++ b/boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h @@ -82,8 +82,8 @@ /** @defgroup STM324x9I_EVAL_SDRAM_Exported_Constants STM324x9I EVAL SDRAM Exported Constants * @{ */ -#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) -#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ +#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000) +#define SDRAM_DEVICE_SIZE ((gU32)0x800000) /* SDRAM device size in MBytes */ /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */ @@ -92,9 +92,9 @@ #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 /* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ -#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */ +#define REFRESH_COUNT ((gU32)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */ -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) +#define SDRAM_TIMEOUT ((gU32)0xFFFF) /* DMA definitions for SDRAM DMA transfer */ #define __DMAx_CLK_ENABLE __DMA2_CLK_ENABLE @@ -106,17 +106,17 @@ /** * @brief FMC SDRAM Mode definition register defines */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200) /** * @} */ @@ -131,13 +131,13 @@ /** @defgroup STM324x9I_EVAL_SDRAM_Exported_Functions STM324x9I EVAL SDRAM Exported Functions * @{ */ -uint8_t BSP_SDRAM_Init(void); -void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); -uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); -uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); +gU8 BSP_SDRAM_Init(void); +void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount); +gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize); +gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize); +gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize); +gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize); +gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); void BSP_SDRAM_DMA_IRQHandler(void); /** diff --git a/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c b/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c index 63df499b..76771e8e 100644 --- a/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c +++ b/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c @@ -71,11 +71,11 @@ #include "stm32f4xx.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ + #define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -135,8 +135,8 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 16000000; - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + gU32 SystemCoreClock = 16000000; + __I gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -173,19 +173,19 @@ void SystemInit(void) #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; + RCC->CR |= (gU32)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + RCC->CR &= (gU32)0xFEF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (gU32)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; @@ -240,7 +240,7 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -299,10 +299,10 @@ void SystemCoreClockUpdate(void) */ void SystemInit_ExtMemCtl(void) { - __IO uint32_t tmp = 0x00; + __IO gU32 tmp = 0x00; - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; + register gU32 tmpreg = 0, timeout = 0xFFFF; + register __IO gU32 index; /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; @@ -464,8 +464,8 @@ void SystemInit_ExtMemCtl(void) { #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #if defined (DATA_IN_ExtSDRAM) - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; + register gU32 tmpreg = 0, timeout = 0xFFFF; + register __IO gU32 index; /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ |