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| author | inmarket <andrewh@inmarket.com.au> | 2018-02-24 11:49:30 +1000 |
|---|---|---|
| committer | inmarket <andrewh@inmarket.com.au> | 2018-02-24 11:49:30 +1000 |
| commit | aeef03a83e59745f06d9b30a5dbbc4eea7170df5 (patch) | |
| tree | 6b79eb91ba4cf8704a955a24b362fd60017b52ca /boards/base/STM32F746-Discovery | |
| parent | 891b78a62c5f65163f81e39b3fa679210611f1d6 (diff) | |
| download | uGFX-aeef03a83e59745f06d9b30a5dbbc4eea7170df5.tar.gz uGFX-aeef03a83e59745f06d9b30a5dbbc4eea7170df5.tar.bz2 uGFX-aeef03a83e59745f06d9b30a5dbbc4eea7170df5.zip | |
Updates to standard STM32LTDC based boards to ensure the LTDC clock is fully operational before continuing
Diffstat (limited to 'boards/base/STM32F746-Discovery')
| -rw-r--r-- | boards/base/STM32F746-Discovery/board_STM32LTDC.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index 8ad0dfa4..55a322b6 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -450,6 +450,7 @@ static GFXINLINE void init_board(GDisplay *g) { RCC->PLLSAICFGR = ((STM32_PLLSAIP_VALUE/2-1)<<16) | (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST; RCC->CR |= RCC_CR_PLLSAION; + while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock #endif // Initialise the SDRAM |