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| author | Dean Camera <dean@fourwalledcubicle.com> | 2011-12-23 01:51:39 +0000 |
|---|---|---|
| committer | Dean Camera <dean@fourwalledcubicle.com> | 2011-12-23 01:51:39 +0000 |
| commit | f201f6697b7f99b63389509b42112026b8f6f76f (patch) | |
| tree | 9f38b5271f3a5ff10083f4f3e27598ced92efe11 /LUFA/Platform/UC3/ClockManagement.h | |
| parent | 77f354609f0411fb6541da31a889186ad402838e (diff) | |
| download | lufa-f201f6697b7f99b63389509b42112026b8f6f76f.tar.gz lufa-f201f6697b7f99b63389509b42112026b8f6f76f.tar.bz2 lufa-f201f6697b7f99b63389509b42112026b8f6f76f.zip | |
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Diffstat (limited to 'LUFA/Platform/UC3/ClockManagement.h')
| -rw-r--r-- | LUFA/Platform/UC3/ClockManagement.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/LUFA/Platform/UC3/ClockManagement.h b/LUFA/Platform/UC3/ClockManagement.h index bb5679ad9..ef2a1b56e 100644 --- a/LUFA/Platform/UC3/ClockManagement.h +++ b/LUFA/Platform/UC3/ClockManagement.h @@ -55,7 +55,7 @@ * { * // Start the master external oscillator which will be used as the main clock reference * AVR32CLK_StartExternalOscillator(0, EXOSC_MODE_8MHZ_OR_MORE, EXOSC_START_0CLK); - * + * * // Start the PLL for the CPU clock, switch CPU to it * AVR32CLK_StartPLL(0, CLOCK_SRC_OSC0, 12000000, F_CPU); * AVR32CLK_SetCPUClockSource(CLOCK_SRC_PLL0, F_CPU); @@ -88,7 +88,7 @@ EXOSC_MODE_900KHZ_MAX = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0, /**< External crystal oscillator equal to or slower than 900KHz. */ EXOSC_MODE_3MHZ_MAX = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1, /**< External crystal oscillator equal to or slower than 3MHz. */ EXOSC_MODE_8MHZ_MAX = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2, /**< External crystal oscillator equal to or slower than 8MHz. */ - EXOSC_MODE_8MHZ_OR_MORE = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3, /**< External crystal oscillator equal to or faster than 8MHz. */ + EXOSC_MODE_8MHZ_OR_MORE = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3, /**< External crystal oscillator equal to or faster than 8MHz. */ }; /** Enum for the possible external oscillator statup times. */ @@ -102,7 +102,7 @@ EXOSC_START_8192CLK = AVR32_PM_OSCCTRL0_STARTUP_8192_RCOSC, /**< Wait 8192 clock cyles before startup for stability. */ EXOSC_START_16384CLK = AVR32_PM_OSCCTRL0_STARTUP_16384_RCOSC, /**< Wait 16384 clock cyles before startup for stability. */ }; - + /** Enum for the possible module clock sources. */ enum UC3_System_ClockSource_t { @@ -182,7 +182,7 @@ { if (SourceFreq > Frequency) return false; - + switch (Source) { case CLOCK_SRC_OSC0: @@ -212,7 +212,7 @@ { AVR32_PM.PLL[Channel].pllen = false; } - + /** Starts the given Generic Clock of the UC3 microcontroller, with the given options. * * \param[in] Channel Index of the Generic Clock to start. @@ -252,17 +252,17 @@ default: return false; } - + if (SourceFreq < Frequency) return false; AVR32_PM.GCCTRL[Channel].diven = (SourceFreq > Frequency) ? true : false; AVR32_PM.GCCTRL[Channel].div = (((SourceFreq / Frequency) - 1) / 2); AVR32_PM.GCCTRL[Channel].cen = true; - + return true; } - + /** Stops the given generic clock of the UC3 microcontroller. * * \param[in] Channel Index of the generic clock to stop. @@ -272,7 +272,7 @@ { AVR32_PM.GCCTRL[Channel].cen = false; } - + /** Sets the clock source for the main microcontroller core. The given clock source should be configured * and ready for use before this function is called. * @@ -310,7 +310,7 @@ default: return false; } - + return true; } @@ -322,3 +322,4 @@ #endif /** @} */ + |