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* More ADCv4 code.Giovanni Di Sirio2018-01-125-672/+325
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* update SDMMC driver and added test hal projectareviu2018-01-1129-155/+3107
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11263 ↵Giovanni Di Sirio2018-01-114-166/+96
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* Added STM32 ADCv4 placeholders.Giovanni Di Sirio2018-01-116-3/+1849
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* Added RTC and WDG support to H7.Giovanni Di Sirio2018-01-113-4/+14
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* ST time source is now configurable between PIT, TC0 and TC1.isiora2018-01-101-0/+102
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* Init PMC and Matrix only if SAMA_HAL_IS_SECURE is true.isiora2018-01-101-2/+3
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* Added ST driver settingsisiora2018-01-101-0/+7
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* SECUMOD Demoedolomb2018-01-1010-0/+1939
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* Enabled ARM cycle counteredolomb2018-01-101-0/+9
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* PORT_SUPPORTS_RT for Cortex-A5 and Cortex-A9edolomb2018-01-101-1/+24
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* Changed memory from 64 KB to 128 KBedolomb2018-01-101-2/+2
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* Clearing pending interrupts in aicInit()edolomb2018-01-101-0/+41
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* Added INTERRUPT SOURCE TYPE mode macrosedolomb2018-01-101-0/+27
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* Included sama_secumod.hedolomb2018-01-101-0/+1
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* Added SECUMOD driveredolomb2018-01-101-0/+1
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* Added pmc functions for SECUMODedolomb2018-01-101-0/+14
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* SECUMOD Driveredolomb2018-01-102-0/+1122
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* SPIv1 and SPIv2 circular mode added. Rework of RCC files and all ↵Giovanni Di Sirio2018-01-1070-1546/+972
| | | | | | dependencies inside STM32 drivers. Documentation fixes in some HAL modules. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11247 35acf78f-673a-0410-8e92-d51de3d6d3f4
* Enabled ARM cycle counteredolomb2018-01-101-0/+9
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* PORT_SUPPORTS_RT for Cortex-A5 and Cortex-A9edolomb2018-01-101-1/+24
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* Polled exchange added to SPIv3.Giovanni Di Sirio2018-01-102-22/+32
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* Added checks related to SPI circular mode.Giovanni Di Sirio2018-01-092-0/+5
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11242 ↵Giovanni Di Sirio2018-01-097-41/+326
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* More fixes, ready for testing.Giovanni Di Sirio2018-01-091-55/+88
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* Various fixes in the new STM32F7xx support code.Giovanni Di Sirio2018-01-096-134/+362
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* Added stub of STM32 I2Cv3 driver for STM32H7xx.Giovanni Di Sirio2018-01-086-6/+1636
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* More compiler portability headers.Giovanni Di Sirio2018-01-082-0/+258
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* Undid some changes.Giovanni Di Sirio2018-01-083-0/+29
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* Updated names.Giovanni Di Sirio2018-01-081-4/+4
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* Added SRAMs cache settings to STM32H7 mcuconf.h.Giovanni Di Sirio2018-01-084-1/+63
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* Unified MPU handler.Giovanni Di Sirio2018-01-0815-7/+238
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* Added unified cache handler for Cortex-M devices.Giovanni Di Sirio2018-01-0811-208/+150
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* Added BDMA support to the STM32H7xx port.Giovanni Di Sirio2018-01-0714-255/+1329
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* first draft. initialization workingareviu2018-01-0724-0/+8312
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11230 ↵Giovanni Di Sirio2018-01-061-0/+303
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* Improved scatter file for STM32H743.Giovanni Di Sirio2018-01-061-15/+18
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* Added stub cache handling functions to the STM32 DMAv1 driver.Giovanni Di Sirio2018-01-051-0/+28
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* Added portability include path to the various startup.mk files.Giovanni Di Sirio2018-01-0522-23/+45
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* SPI driver works, probably optimizations are possible.Giovanni Di Sirio2018-01-054-6/+12
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* Added Region Maskedolomb2018-01-041-10/+55
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* Fixed mtxRegionXXX macros.isiora2018-01-041-2/+2
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* Yet another problem fixed, now it starts to output data, still problems.Giovanni Di Sirio2018-01-041-1/+2
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* Fixed wrong CS.Giovanni Di Sirio2018-01-041-6/+6
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* More fixes but SPIv3 still does not work.Giovanni Di Sirio2018-01-042-19/+13
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* Various fixes, H7 SPI does not work yet.Giovanni Di Sirio2018-01-044-15/+12
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11219 ↵edolomb2018-01-041-3/+3
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* Added Matrix MACROsedolomb2018-01-041-1/+183
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* Added H7 builder to the STM32 SPI unified demo.Giovanni Di Sirio2018-01-049-15/+1962
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* git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11216 ↵Giovanni Di Sirio2018-01-031-0/+3
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generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 20:15:03 +0000