diff options
Diffstat (limited to 'os/hal/platforms/SPC560BCxx/hal_lld.h')
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/hal_lld.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h index 701e2f4a7..d92fb53bf 100644 --- a/os/hal/platforms/SPC560BCxx/hal_lld.h +++ b/os/hal/platforms/SPC560BCxx/hal_lld.h @@ -284,6 +284,30 @@ #endif
/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL1_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
* @brief Active run modes in ME_ME register.
* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
* is no need to specify them.
@@ -678,6 +702,36 @@ #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
#endif
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PHERIPERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PHERIPERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PHERIPERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PHERIPERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PHERIPERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PHERIPERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PHERIPERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PHERIPERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PHERIPERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PHERIPERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PHERIPERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PHERIPERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL3_CLK_DIV_VALUE value specified"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
|