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-rw-r--r--docs/reports/SPC560B50-64.txt22
-rw-r--r--os/hal/platforms/SPC560BCxx/hal_lld.c5
-rw-r--r--os/hal/platforms/SPC560BCxx/hal_lld.h54
-rw-r--r--os/hal/platforms/SPC560BCxx/spc560bc_registry.h4
4 files changed, 74 insertions, 11 deletions
diff --git a/docs/reports/SPC560B50-64.txt b/docs/reports/SPC560B50-64.txt
index ad7e790ca..b5c60ee05 100644
--- a/docs/reports/SPC560B50-64.txt
+++ b/docs/reports/SPC560B50-64.txt
@@ -6,7 +6,7 @@ Settings: SYSCLK=64
*** ChibiOS/RT test suite
***
*** Kernel: 2.5.2unstable
-*** Compiled: Feb 15 2013 - 12:24:06
+*** Compiled: Feb 19 2013 - 11:15:43
*** Compiler: GCC 4.6.3 build on 2013-01-07
*** Architecture: Power Architecture
*** Core Variant: e200z0
@@ -100,7 +100,7 @@ Settings: SYSCLK=64
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 200707 msgs/S, 401414 ctxswc/S
+--- Score : 200701 msgs/S, 401402 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
@@ -108,23 +108,23 @@ Settings: SYSCLK=64
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 167515 msgs/S, 335030 ctxswc/S
+--- Score : 167519 msgs/S, 335038 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
---- Score : 590272 ctxswc/S
+--- Score : 590288 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 132964 threads/S
+--- Score : 132967 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 189949 threads/S
+--- Score : 189947 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 51973 reschedules/S, 311838 ctxswc/S
+--- Score : 51972 reschedules/S, 311832 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
@@ -132,19 +132,19 @@ Settings: SYSCLK=64
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 619272 bytes/S
+--- Score : 619280 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 802792 timers/S
+--- Score : 802802 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 818236 wait+signal/S
+--- Score : 818244 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 643052 lock+unlock/S
+--- Score : 643028 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c
index aa4c7f538..c24eb1ee1 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.c
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.c
@@ -144,6 +144,11 @@ void spc_clock_init(void) {
CGM.OSC_CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
+ CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
+ CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
+
/* Initialization of the FMPLLs settings.*/
CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
index 701e2f4a7..d92fb53bf 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.h
@@ -284,6 +284,30 @@
#endif
/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL1_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
* @brief Active run modes in ME_ME register.
* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
* is no need to specify them.
@@ -678,6 +702,36 @@
#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
#endif
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PHERIPERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PHERIPERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PHERIPERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PHERIPERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PHERIPERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PHERIPERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PHERIPERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PHERIPERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PHERIPERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PHERIPERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PHERIPERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PHERIPERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL3_CLK_DIV_VALUE value specified"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
index 39563dbd1..417b73912 100644
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
@@ -40,6 +40,8 @@
#define SPC5_LINFLEX0_RXI_NUMBER 79
#define SPC5_LINFLEX0_TXI_NUMBER 80
#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_PHERIPERAL1_CLK_DIV_VALUE)
#define SPC5_HAS_LINFLEX1 TRUE
#define SPC5_LINFLEX1_PCTL 49
@@ -49,6 +51,8 @@
#define SPC5_LINFLEX1_RXI_NUMBER 99
#define SPC5_LINFLEX1_TXI_NUMBER 100
#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_PHERIPERAL1_CLK_DIV_VALUE)
#define SPC5_HAS_LINFLEX2 TRUE
#define SPC5_LINFLEX2_PCTL 50
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 12:02:19 +0000