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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-10-07 09:22:10 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-10-07 09:22:10 +0000
commit40932b20589b66407578a84eb573dd0bfc5395cd (patch)
tree0068560c4728634acb6af9826fd2e6bf9768ce4c /tools
parent0f2e8f0b01edd1a0389426b316f491acf49af596 (diff)
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Enabled TRNG on L4+.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12344 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'tools')
-rw-r--r--tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl7
1 files changed, 6 insertions, 1 deletions
diff --git a/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
index 59508f676..652b2342e 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
@@ -105,7 +105,7 @@
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
-#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}
+#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1"}
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
#define STM32_DFSDMSEL ${doc.STM32_DFSDMSEL!"STM32_DFSDMSEL_PCLK2"}
#define STM32_ADFSDMSEL ${doc.STM32_ADFSDMSEL!"STM32_ADFSDMSEL_SAI1CLK"}
@@ -283,6 +283,11 @@
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
/*
+ * TRNG driver system settings.
+ */
+#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
+
+/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}