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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-09-22 15:27:12 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-09-22 15:27:12 +0000
commitc708f7d750f2190ff82075378965214c06437d8c (patch)
tree430e2d36abfdb6bd4a4b22094e22d9cd7e78a26d /testhal
parent7c9ad610a6068f7ee292f8259cdcd7488391a60a (diff)
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USARTv2 made DMAMUX-aware.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12281 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'testhal')
-rw-r--r--testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
index 759132c05..116c9ac92 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -272,10 +272,39 @@
/*
* UART driver system settings.
*/
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USART1_RX_DMA_CHANNEL 13
+#define STM32_UART_USART1_TX_DMA_CHANNEL 0
+#define STM32_UART_USART2_RX_DMA_CHANNEL 1
+#define STM32_UART_USART2_TX_DMA_CHANNEL 2
+#define STM32_UART_USART3_RX_DMA_CHANNEL 3
+#define STM32_UART_USART3_TX_DMA_CHANNEL 4
+#define STM32_UART_UART4_RX_DMA_CHANNEL 5
+#define STM32_UART_UART4_TX_DMA_CHANNEL 6
+#define STM32_UART_UART5_RX_DMA_CHANNEL 7
+#define STM32_UART_UART5_TX_DMA_CHANNEL 8
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
/*
* WDG driver system settings.