USARTv2 made DMAMUX-aware.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12281 110e8d01-0319-4d1e-a829-52ad28d1bb01

10 files changed, 323 insertions, 13 deletions

diff --git a/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h
index 9bc513354..1f17b586f 100644
--- a/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h
@@ -297,7 +297,6 @@
 #define STM32_UART_USE_USART3               FALSE

 #define STM32_UART_USE_UART4                FALSE

 #define STM32_UART_USE_UART5                FALSE

-#define STM32_UART_USE_LPUART1              FALSE

 #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

 #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)

 #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

@@ -308,8 +307,6 @@
 #define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)

 #define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 2)

 #define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 1)

-#define STM32_UART_LPUART1_RX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 7)

-#define STM32_UART_LPUART1_TX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 6)

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

 #define STM32_UART_USART3_IRQ_PRIORITY      12

@@ -320,7 +317,6 @@
 #define STM32_UART_USART3_DMA_PRIORITY      0

 #define STM32_UART_UART4_DMA_PRIORITY       0

 #define STM32_UART_UART5_DMA_PRIORITY       0

-#define STM32_UART_LPUART1_DMA_PRIORITY     0

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

 

 /*

diff --git a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
index 13621ef1f..00df41989 100644
--- a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
@@ -272,10 +272,39 @@
 /*

  * UART driver system settings.

  */

+#define STM32_UART_USE_USART1               FALSE

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USE_UART4                FALSE

+#define STM32_UART_USE_UART5                FALSE

+#define STM32_UART_USART1_RX_DMA_CHANNEL    13

+#define STM32_UART_USART1_TX_DMA_CHANNEL    0

+#define STM32_UART_USART2_RX_DMA_CHANNEL    1

+#define STM32_UART_USART2_TX_DMA_CHANNEL    2

+#define STM32_UART_USART3_RX_DMA_CHANNEL    3

+#define STM32_UART_USART3_TX_DMA_CHANNEL    4

+#define STM32_UART_UART4_RX_DMA_CHANNEL     5

+#define STM32_UART_UART4_TX_DMA_CHANNEL     6

+#define STM32_UART_UART5_RX_DMA_CHANNEL     7

+#define STM32_UART_UART5_TX_DMA_CHANNEL     8

+#define STM32_UART_USART1_IRQ_PRIORITY      12

+#define STM32_UART_USART2_IRQ_PRIORITY      12

+#define STM32_UART_USART3_IRQ_PRIORITY      12

+#define STM32_UART_UART4_IRQ_PRIORITY       12

+#define STM32_UART_UART5_IRQ_PRIORITY       12

+#define STM32_UART_USART1_DMA_PRIORITY      0

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_UART4_DMA_PRIORITY       0

+#define STM32_UART_UART5_DMA_PRIORITY       0

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

 

 /*

  * USB driver system settings.

  */

+#define STM32_USB_USE_OTG1                  FALSE

+#define STM32_USB_OTG1_IRQ_PRIORITY         14

+#define STM32_USB_OTG1_RX_FIFO_SIZE         512

 

 /*

  * WDG driver system settings.

diff --git a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
index 43fd676e2..c1cdf3c54 100644
--- a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
+++ b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.h
@@ -304,6 +304,38 @@
 /* Devices with DMAMUX require a different kind of check.*/

 #if STM32_DMA_SUPPORTS_DMAMUX

 

+/* Check on the presence of the DMA channel settings in mcuconf.h.*/

+#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_CHANNEL) ||       \

+                           !defined(STM32_SPI_SPI1_TX_DMA_CHANNEL))

+#error "SPI1 DMA channels not defined"

+#endif

+

+#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_CHANNEL) ||       \

+                           !defined(STM32_SPI_SPI2_TX_DMA_CHANNEL))

+#error "SPI2 DMA streams not defined"

+#endif

+

+#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_CHANNEL) ||       \

+                           !defined(STM32_SPI_SPI3_TX_DMA_CHANNEL))

+#error "SPI3 DMA streams not defined"

+#endif

+

+#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_CHANNEL) ||       \

+                           !defined(STM32_SPI_SPI4_TX_DMA_CHANNEL))

+#error "SPI4 DMA streams not defined"

+#endif

+

+#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_CHANNEL) ||       \

+                           !defined(STM32_SPI_SPI5_TX_DMA_CHANNEL))

+#error "SPI5 DMA streams not defined"

+#endif

+

+#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_CHANNEL) ||       \

+                           !defined(STM32_SPI_SPI6_TX_DMA_CHANNEL))

+#error "SPI6 DMA streams not defined"

+#endif

+

+/* Check on the validity of the assigned DMA channels.*/

 #if STM32_SPI_USE_SPI1 &&                                                   \

     !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_TX_DMA_CHANNEL)

 #error "Invalid DMA channel assigned to SPI1 TX"

diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
index 214786cab..631371e5c 100644
--- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
@@ -594,8 +594,13 @@ void uart_lld_init(void) {
   UARTD1.usart   = USART1;

   UARTD1.clock   = STM32_USART1CLK;

   UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_CHANNEL);

+  UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_CHANNEL);

+#else

   UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);

   UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);

+#endif

 #if defined(STM32_USART1_NUMBER)

   nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);

 #endif

@@ -606,8 +611,13 @@ void uart_lld_init(void) {
   UARTD2.usart   = USART2;

   UARTD2.clock   = STM32_USART2CLK;

   UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_CHANNEL);

+  UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_CHANNEL);

+#else

   UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);

   UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);

+#endif

 #if defined(STM32_USART2_NUMBER)

   nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);

 #endif

@@ -618,8 +628,13 @@ void uart_lld_init(void) {
   UARTD3.usart   = USART3;

   UARTD3.clock   = STM32_USART3CLK;

   UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_CHANNEL);

+  UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_CHANNEL);

+#else

   UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);

   UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);

+#endif

 #if defined(STM32_USART3_NUMBER)

   nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);

 #endif

@@ -630,8 +645,13 @@ void uart_lld_init(void) {
   UARTD4.usart   = UART4;

   UARTD4.clock   = STM32_UART4CLK;

   UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD4.dmarx   = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_CHANNEL);

+  UARTD4.dmatx   = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_CHANNEL);

+#else

   UARTD4.dmarx   = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);

   UARTD4.dmatx   = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);

+#endif

 #if defined(STM32_UART4_NUMBER)

   nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);

 #endif

@@ -642,8 +662,13 @@ void uart_lld_init(void) {
   UARTD5.usart   = UART5;

   UARTD5.clock   = STM32_UART5CLK;

   UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD5.dmarx   = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_CHANNEL);

+  UARTD5.dmatx   = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_CHANNEL);

+#else

   UARTD5.dmarx   = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);

   UARTD5.dmatx   = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);

+#endif

 #if defined(STM32_UART5_NUMBER)

   nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);

 #endif

@@ -654,8 +679,13 @@ void uart_lld_init(void) {
   UARTD6.usart   = USART6;

   UARTD6.clock   = STM32_USART6CLK;

   UARTD6.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD6.dmarx   = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_CHANNEL);

+  UARTD6.dmatx   = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_CHANNEL);

+#else

   UARTD6.dmarx   = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);

   UARTD6.dmatx   = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);

+#endif

 #if defined(STM32_USART6_NUMBER)

   nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);

 #endif

@@ -666,8 +696,13 @@ void uart_lld_init(void) {
   UARTD7.usart   = UART7;

   UARTD7.clock   = STM32_UART7CLK;

   UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD7.dmarx   = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_CHANNEL);

+  UARTD7.dmatx   = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_CHANNEL);

+#else

   UARTD7.dmarx   = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_STREAM);

   UARTD7.dmatx   = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_STREAM);

+#endif

 #if defined(STM32_UART7_NUMBER)

   nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY);

 #endif

@@ -678,8 +713,13 @@ void uart_lld_init(void) {
   UARTD8.usart   = UART8;

   UARTD8.clock   = STM32_UART8CLK;

   UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+#if STM32_DMA_SUPPORTS_DMAMUX

+  UARTD8.dmarx   = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_CHANNEL);

+  UARTD8.dmatx   = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_CHANNEL);

+#else

   UARTD8.dmarx   = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_STREAM);

   UARTD8.dmatx   = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_STREAM);

+#endif

 #if defined(STM32_UART8_NUMBER)

   nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY);

 #endif

@@ -720,6 +760,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUSART1(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART1_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART1_TX);

+#endif

     }

 #endif

 

@@ -739,6 +783,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUSART2(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART2_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART2_TX);

+#endif

     }

 #endif

 

@@ -758,6 +806,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUSART3(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART3_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART3_TX);

+#endif

     }

 #endif

 

@@ -777,6 +829,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUART4(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART4_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART4_TX);

+#endif

     }

 #endif

 

@@ -796,6 +852,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUART5(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART5_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART5_TX);

+#endif

     }

 #endif

 

@@ -815,6 +875,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUSART6(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART6_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART6_TX);

+#endif

     }

 #endif

 

@@ -834,6 +898,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUART7(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART7_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART7_TX);

+#endif

     }

 #endif

 

@@ -853,6 +921,10 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUART8(true);

       uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |

                         STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);

+#if STM32_DMA_SUPPORTS_DMAMUX

+      dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART8_RX);

+      dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART8_TX);

+#endif

     }

 #endif

 

diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
index 6a28405eb..6e7c09cc8 100644
--- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
+++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
@@ -397,9 +397,133 @@
 #error "Invalid DMA priority assigned to UART8"

 #endif

 

-/* The following checks are only required when there is a DMA able to

-   reassign streams to different channels.*/

-#if STM32_ADVANCED_DMA

+/* Devices with DMAMUX require a different kind of check.*/

+#if STM32_DMA_SUPPORTS_DMAMUX

+

+/* Check on the presence of the DMA channel settings in mcuconf.h.*/

+#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_CHANNEL) || \

+                              !defined(STM32_UART_USART1_TX_DMA_CHANNEL))

+#error "USART1 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_CHANNEL) || \

+                              !defined(STM32_UART_USART2_TX_DMA_CHANNEL))

+#error "USART2 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_CHANNEL) || \

+                              !defined(STM32_UART_USART3_TX_DMA_CHANNEL))

+#error "USART3 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_CHANNEL) ||   \

+                             !defined(STM32_UART_UART4_TX_DMA_CHANNEL))

+#error "UART4 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_CHANNEL) ||   \

+                             !defined(STM32_UART_UART5_TX_DMA_CHANNEL))

+#error "UART5 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_CHANNEL) || \

+                              !defined(STM32_UART_USART6_TX_DMA_CHANNEL))

+#error "USART6 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_UART7 && (!defined(STM32_UART_UART7_RX_DMA_CHANNEL) ||   \

+                             !defined(STM32_UART_UART7_TX_DMA_CHANNEL))

+#error "UART7 DMA channels not defined"

+#endif

+

+#if STM32_UART_USE_UART8 && (!defined(STM32_UART_UART8_RX_DMA_CHANNEL) ||   \

+                             !defined(STM32_UART_UART8_TX_DMA_CHANNEL))

+#error "UART8 DMA channels not defined"

+#endif

+

+/* Check on the validity of the assigned DMA channels.*/

+#if STM32_UART_USE_USART1 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART1_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART1 RX"

+#endif

+

+#if STM32_UART_USE_USART1 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART1_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART1 TX"

+#endif

+

+#if STM32_UART_USE_USART2 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART2_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART2 RX"

+#endif

+

+#if STM32_UART_USE_USART2 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART2_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART2 TX"

+#endif

+

+#if STM32_UART_USE_USART3 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART3_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART3 RX"

+#endif

+

+#if STM32_UART_USE_USART3 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART3_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART3 TX"

+#endif

+

+#if STM32_UART_USE_UART4 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART4_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART4 RX"

+#endif

+

+#if STM32_UART_USE_UART4 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART4_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART4 TX"

+#endif

+

+#if STM32_UART_USE_UART5 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART5_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART5 RX"

+#endif

+

+#if STM32_UART_USE_UART5 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART5_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART5 TX"

+#endif

+

+#if STM32_UART_USE_USART6 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART6_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART6 RX"

+#endif

+

+#if STM32_UART_USE_USART6 &&                                                \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_USART6_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to USART6 TX"

+#endif

+

+#if STM32_UART_USE_UART7 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART7_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART7 RX"

+#endif

+

+#if STM32_UART_USE_UART7 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART7_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART7 TX"

+#endif

+

+#if STM32_UART_USE_UART8 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART8_RX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART8 RX"

+#endif

+

+#if STM32_UART_USE_UART8 &&                                                 \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_UART_UART8_TX_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to UART8 TX"

+#endif

+

+#else /* !STM32_DMA_SUPPORTS_DMAMUX */

+

 /* Check on the presence of the DMA streams settings in mcuconf.h.*/

 #if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) ||  \

                               !defined(STM32_UART_USART1_TX_DMA_STREAM))

@@ -537,7 +661,8 @@
                            STM32_UART8_TX_DMA_MSK)

 #error "invalid DMA stream associated to UART8 TX"

 #endif

-#endif /* STM32_ADVANCED_DMA */

+

+#endif /* !STM32_DMA_SUPPORTS_DMAMUX */

 

 #if !defined(STM32_DMA_REQUIRED)

 #define STM32_DMA_REQUIRED

diff --git a/os/hal/ports/STM32/STM32L4xx+/platform.mk b/os/hal/ports/STM32/STM32L4xx+/platform.mk
index dba1d5516..d4b905ea0 100644
--- a/os/hal/ports/STM32/STM32L4xx+/platform.mk
+++ b/os/hal/ports/STM32/STM32L4xx+/platform.mk
@@ -31,6 +31,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
 include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk

 include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk

 include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk

+include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk

 include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk

 

 # Shared variables

diff --git a/readme.txt b/readme.txt
index c0fccd8c9..fcf0869f3 100644
--- a/readme.txt
+++ b/readme.txt
@@ -93,7 +93,8 @@
 *** Next ***

 - NEW: Added mcuconf.h generators for STM32L496xx and STM32L4R5xx devices.

 - NEW: Added demo for STM32L496ZG-Nucleo144 and STM32L4R5ZI-Nucleo144 boards.

-- NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2 and SPIv2 are now DMAMUX-aware.

+- NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2, SPIv2 and USARTv2 are now

+       DMAMUX-aware.

 - NEW: Introduced support for STM32L4+ devices.

 - NEW: Independent TRNG driver model added to HAL.

 - NEW: TRNG API now takes a new "size" parameter, the API can now generate

diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
index 759132c05..116c9ac92 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -272,10 +272,39 @@
 /*

  * UART driver system settings.

  */

+#define STM32_UART_USE_USART1               FALSE

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USE_UART4                FALSE

+#define STM32_UART_USE_UART5                FALSE

+#define STM32_UART_USART1_RX_DMA_CHANNEL    13

+#define STM32_UART_USART1_TX_DMA_CHANNEL    0

+#define STM32_UART_USART2_RX_DMA_CHANNEL    1

+#define STM32_UART_USART2_TX_DMA_CHANNEL    2

+#define STM32_UART_USART3_RX_DMA_CHANNEL    3

+#define STM32_UART_USART3_TX_DMA_CHANNEL    4

+#define STM32_UART_UART4_RX_DMA_CHANNEL     5

+#define STM32_UART_UART4_TX_DMA_CHANNEL     6

+#define STM32_UART_UART5_RX_DMA_CHANNEL     7

+#define STM32_UART_UART5_TX_DMA_CHANNEL     8

+#define STM32_UART_USART1_IRQ_PRIORITY      12

+#define STM32_UART_USART2_IRQ_PRIORITY      12

+#define STM32_UART_USART3_IRQ_PRIORITY      12

+#define STM32_UART_UART4_IRQ_PRIORITY       12

+#define STM32_UART_UART5_IRQ_PRIORITY       12

+#define STM32_UART_USART1_DMA_PRIORITY      0

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_UART4_DMA_PRIORITY       0

+#define STM32_UART_UART5_DMA_PRIORITY       0

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

 

 /*

  * USB driver system settings.

  */

+#define STM32_USB_USE_OTG1                  FALSE

+#define STM32_USB_OTG1_IRQ_PRIORITY         14

+#define STM32_USB_OTG1_RX_FIFO_SIZE         512

 

 /*

  * WDG driver system settings.

diff --git a/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl
index d307f57e6..6a0dd567a 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl
@@ -308,7 +308,6 @@
 #define STM32_UART_USE_USART3               ${doc.STM32_UART_USE_USART3!"FALSE"}

 #define STM32_UART_USE_UART4                ${doc.STM32_UART_USE_UART4!"FALSE"}

 #define STM32_UART_USE_UART5                ${doc.STM32_UART_USE_UART5!"FALSE"}

-#define STM32_UART_USE_LPUART1              ${doc.STM32_UART_USE_LPUART1!"FALSE"}

 #define STM32_UART_USART1_RX_DMA_STREAM     ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

 #define STM32_UART_USART1_TX_DMA_STREAM     ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}

 #define STM32_UART_USART2_RX_DMA_STREAM     ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}

@@ -319,8 +318,6 @@
 #define STM32_UART_UART4_TX_DMA_STREAM      ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}

 #define STM32_UART_UART5_RX_DMA_STREAM      ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}

 #define STM32_UART_UART5_TX_DMA_STREAM      ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}

-#define STM32_UART_LPUART1_RX_DMA_STREAM    ${doc.STM32_UART_LPUART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

-#define STM32_UART_LPUART1_TX_DMA_STREAM    ${doc.STM32_UART_LPUART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}

 #define STM32_UART_USART1_IRQ_PRIORITY      ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}

 #define STM32_UART_USART2_IRQ_PRIORITY      ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}

 #define STM32_UART_USART3_IRQ_PRIORITY      ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}

@@ -331,7 +328,6 @@
 #define STM32_UART_USART3_DMA_PRIORITY      ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}

 #define STM32_UART_UART4_DMA_PRIORITY       ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}

 #define STM32_UART_UART5_DMA_PRIORITY       ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}

-#define STM32_UART_LPUART1_DMA_PRIORITY     ${doc.STM32_UART_LPUART1_DMA_PRIORITY!"0"}

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}

 

 /*

diff --git a/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl
index 424d8081c..74613ac59 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl
@@ -283,10 +283,39 @@
 /*

  * UART driver system settings.

  */

+#define STM32_UART_USE_USART1               ${doc.STM32_UART_USE_USART1!"FALSE"}

+#define STM32_UART_USE_USART2               ${doc.STM32_UART_USE_USART2!"FALSE"}

+#define STM32_UART_USE_USART3               ${doc.STM32_UART_USE_USART3!"FALSE"}

+#define STM32_UART_USE_UART4                ${doc.STM32_UART_USE_UART4!"FALSE"}

+#define STM32_UART_USE_UART5                ${doc.STM32_UART_USE_UART5!"FALSE"}

+#define STM32_UART_USART1_RX_DMA_CHANNEL    ${doc.STM32_UART_USART1_RX_DMA_CHANNEL!"13"}

+#define STM32_UART_USART1_TX_DMA_CHANNEL    ${doc.STM32_UART_USART1_TX_DMA_CHANNEL!"0"}

+#define STM32_UART_USART2_RX_DMA_CHANNEL    ${doc.STM32_UART_USART2_RX_DMA_CHANNEL!"1"}

+#define STM32_UART_USART2_TX_DMA_CHANNEL    ${doc.STM32_UART_USART2_TX_DMA_CHANNEL!"2"}

+#define STM32_UART_USART3_RX_DMA_CHANNEL    ${doc.STM32_UART_USART3_RX_DMA_CHANNEL!"3"}

+#define STM32_UART_USART3_TX_DMA_CHANNEL    ${doc.STM32_UART_USART3_TX_DMA_CHANNEL!"4"}

+#define STM32_UART_UART4_RX_DMA_CHANNEL     ${doc.STM32_UART_UART4_RX_DMA_CHANNEL!"5"}

+#define STM32_UART_UART4_TX_DMA_CHANNEL     ${doc.STM32_UART_UART4_TX_DMA_CHANNEL!"6"}

+#define STM32_UART_UART5_RX_DMA_CHANNEL     ${doc.STM32_UART_UART5_RX_DMA_CHANNEL!"7"}

+#define STM32_UART_UART5_TX_DMA_CHANNEL     ${doc.STM32_UART_UART5_TX_DMA_CHANNEL!"8"}

+#define STM32_UART_USART1_IRQ_PRIORITY      ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART2_IRQ_PRIORITY      ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART3_IRQ_PRIORITY      ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}

+#define STM32_UART_UART4_IRQ_PRIORITY       ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}

+#define STM32_UART_UART5_IRQ_PRIORITY       ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART1_DMA_PRIORITY      ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}

+#define STM32_UART_USART2_DMA_PRIORITY      ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}

+#define STM32_UART_USART3_DMA_PRIORITY      ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}

+#define STM32_UART_UART4_DMA_PRIORITY       ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}

+#define STM32_UART_UART5_DMA_PRIORITY       ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}

 

 /*

  * USB driver system settings.

  */

+#define STM32_USB_USE_OTG1                  ${doc.STM32_USB_USE_OTG1!"FALSE"}

+#define STM32_USB_OTG1_IRQ_PRIORITY         ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}

+#define STM32_USB_OTG1_RX_FIFO_SIZE         ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}

 

 /*

  * WDG driver system settings.