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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-05-27 13:42:33 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-05-27 13:42:33 +0000
commit2b01d72e42576594924aa12fe50571cd56cafbb5 (patch)
treed45beff58f2f862917cb11ad053c97c8f313779f /testhal/STM32F0xx
parent0bc6e6f77fced2bf8db588eb765c78bbf7cf0f20 (diff)
downloadChibiOS-2b01d72e42576594924aa12fe50571cd56cafbb5.tar.gz
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4242 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32F0xx')
-rw-r--r--testhal/STM32F0xx/ADC/Makefile2
-rw-r--r--testhal/STM32F0xx/ADC/main.c17
2 files changed, 10 insertions, 9 deletions
diff --git a/testhal/STM32F0xx/ADC/Makefile b/testhal/STM32F0xx/ADC/Makefile
index e82dcc974..0b2d556fb 100644
--- a/testhal/STM32F0xx/ADC/Makefile
+++ b/testhal/STM32F0xx/ADC/Makefile
@@ -118,7 +118,7 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
# Compiler settings
#
-MCU = cortex-m3
+MCU = cortex-m0
#TRGT = arm-elf-
TRGT = arm-none-eabi-
diff --git a/testhal/STM32F0xx/ADC/main.c b/testhal/STM32F0xx/ADC/main.c
index dba3a5254..6038a2fb2 100644
--- a/testhal/STM32F0xx/ADC/main.c
+++ b/testhal/STM32F0xx/ADC/main.c
@@ -24,7 +24,7 @@
#define ADC_GRP1_NUM_CHANNELS 1
#define ADC_GRP1_BUF_DEPTH 8
-#define ADC_GRP2_NUM_CHANNELS 8
+#define ADC_GRP2_NUM_CHANNELS 4
#define ADC_GRP2_BUF_DEPTH 16
static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
@@ -61,24 +61,25 @@ static const ADCConversionGroup adcgrpcfg1 = {
ADC_GRP1_NUM_CHANNELS,
NULL,
adcerrorcallback,
- 0, /* CFGRR1 */
- 0, /* SMPR */
- 0 /* CHSELR */
+ ADC_CFGR1_RES_12BIT, /* CFGRR1 */
+ ADC_SMPR_SMP_1P5, /* SMPR */
+ ADC_CHSELR_CHSEL10 /* CHSELR */
};
/*
* ADC conversion group.
* Mode: Continuous, 16 samples of 8 channels, SW triggered.
- * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef.
+ * Channels: IN10, IN11, Sensor, VRef.
*/
static const ADCConversionGroup adcgrpcfg2 = {
TRUE,
ADC_GRP2_NUM_CHANNELS,
adccallback,
adcerrorcallback,
- 0, /* CFGRR1 */
- 0, /* SMPR */
- 0 /* CHSELR */
+ ADC_CFGR1_RES_12BIT, /* CFGRR1 */
+ ADC_SMPR_SMP_28P5, /* SMPR */
+ ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 |
+ ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17 /* CHSELR */
};
/*