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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-10-11 18:55:06 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-10-11 18:55:06 +0000
commit441509bc2c585151a5d5974337d6fd2e156eab2a (patch)
treeda3717d5decdd19548c46c8438340d9704140854 /testhal/STM32/SPI
parent7c2a8e13d969029fb675e67c57349c1deaa09284 (diff)
downloadChibiOS-441509bc2c585151a5d5974337d6fd2e156eab2a.tar.gz
ChibiOS-441509bc2c585151a5d5974337d6fd2e156eab2a.tar.bz2
ChibiOS-441509bc2c585151a5d5974337d6fd2e156eab2a.zip
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2247 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32/SPI')
-rw-r--r--testhal/STM32/SPI/main.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/testhal/STM32/SPI/main.c b/testhal/STM32/SPI/main.c
index a8a8595f1..09e3131f9 100644
--- a/testhal/STM32/SPI/main.c
+++ b/testhal/STM32/SPI/main.c
@@ -24,6 +24,7 @@
* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig hs_spicfg = {
+ NULL,
GPIOA,
GPIOA_SPI1NSS,
0
@@ -33,6 +34,7 @@ static const SPIConfig hs_spicfg = {
* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig ls_spicfg = {
+ NULL,
GPIOA,
GPIOA_SPI1NSS,
SPI_CR1_BR_2 | SPI_CR1_BR_1
@@ -56,8 +58,8 @@ static msg_t spi_thread_1(void *p) {
palClearPad(IOPORT3, GPIOC_LED); /* LED ON. */
spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */
spiSelect(&SPID1); /* Slave Select assertion. */
- spiExchange(&SPID1, 512,
- txbuf, rxbuf); /* Atomic transfer operations. */
+ spiExchangeWait(&SPID1, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
spiUnselect(&SPID1); /* Slave Select de-assertion. */
spiReleaseBus(&SPID1); /* Ownership release. */
}
@@ -76,8 +78,8 @@ static msg_t spi_thread_2(void *p) {
palSetPad(IOPORT3, GPIOC_LED); /* LED OFF. */
spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */
spiSelect(&SPID1); /* Slave Select assertion. */
- spiExchange(&SPID1, 512,
- txbuf, rxbuf); /* Atomic transfer operations. */
+ spiExchangeWait(&SPID1, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
spiUnselect(&SPID1); /* Slave Select de-assertion. */
spiReleaseBus(&SPID1); /* Ownership release. */
}