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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-10-11 18:55:06 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-10-11 18:55:06 +0000
commit441509bc2c585151a5d5974337d6fd2e156eab2a (patch)
treeda3717d5decdd19548c46c8438340d9704140854
parent7c2a8e13d969029fb675e67c57349c1deaa09284 (diff)
downloadChibiOS-441509bc2c585151a5d5974337d6fd2e156eab2a.tar.gz
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2247 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--demos/ARMCM3-STM32F103-FATFS-GCC/main.c5
-rw-r--r--os/hal/include/spi.h3
-rw-r--r--os/hal/platforms/STM32/spi_lld.c11
-rw-r--r--os/hal/src/mmc_spi.c30
-rw-r--r--testhal/STM32/SPI/main.c10
5 files changed, 32 insertions, 27 deletions
diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c
index 0802ec7bc..2422f652b 100644
--- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c
+++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c
@@ -46,10 +46,11 @@ MMCDriver MMCD1;
static bool_t fs_ready = FALSE;
/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/
-static SPIConfig hs_spicfg = {IOPORT2, GPIOB_SPI2NSS, 0};
+static SPIConfig hs_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, 0};
/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).*/
-static SPIConfig ls_spicfg = {IOPORT2, GPIOB_SPI2NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1};
+static SPIConfig ls_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS,
+ SPI_CR1_BR_2 | SPI_CR1_BR_1};
/* MMC configuration (empty).*/
static const MMCConfig mmc_cfg = {};
diff --git a/os/hal/include/spi.h b/os/hal/include/spi.h
index fee5742d1..cb13fa605 100644
--- a/os/hal/include/spi.h
+++ b/os/hal/include/spi.h
@@ -221,12 +221,13 @@ typedef enum {
* @notapi
*/
#define _spi_wakeup(spip) { \
+ chSysLockFromIsr(); \
if ((spip)->spd_thread != NULL) { \
Thread *tp = (spip)->spd_thread; \
(spip)->spd_thread = NULL; \
- tp->p_u.rdymsg = RDY_RESET; \
chSchReadyI(tp); \
} \
+ chSysUnlockFromIsr(); \
}
/**
diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index bb69f8c5f..cbb7859a3 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -53,6 +53,9 @@ SPIDriver SPID3;
/* Driver local variables. */
/*===========================================================================*/
+static uint16_t dummytx;
+static uint16_t dummyrx;
+
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@@ -84,7 +87,7 @@ SPIDriver SPID3;
*/
static void serve_interrupt(SPIDriver *spip) {
- /* Stops everything.*/
+ /* Stop everything.*/
dma_stop(spip);
/* If a callback is defined then invokes it.*/
@@ -216,6 +219,8 @@ CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
*/
void spi_lld_init(void) {
+ dummytx = 0xFFFF;
+
#if STM32_SPI_USE_SPI1
RCC->APB2RSTR = RCC_APB2RSTR_SPI1RST;
RCC->APB2RSTR = 0;
@@ -388,8 +393,6 @@ void spi_lld_unselect(SPIDriver *spip) {
* @notapi
*/
void spi_lld_ignore(SPIDriver *spip, size_t n) {
- uint16_t dummyrx;
- uint16_t dummytx = 0xFFFF;
dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,
spip->spd_dmaccr | DMA_CCR1_TCIE);
@@ -437,7 +440,6 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
* @notapi
*/
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
- uint16_t dummyrx;
dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,
spip->spd_dmaccr | DMA_CCR1_TCIE);
@@ -460,7 +462,6 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
* @notapi
*/
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
- uint16_t dummytx = 0xFFFF;
dmaChannelSetup(spip->spd_dmarx, n, rxbuf,
spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC);
diff --git a/os/hal/src/mmc_spi.c b/os/hal/src/mmc_spi.c
index 49f75c3cc..76b710a03 100644
--- a/os/hal/src/mmc_spi.c
+++ b/os/hal/src/mmc_spi.c
@@ -84,13 +84,13 @@ static void wait(MMCDriver *mmcp) {
uint8_t buf[4];
for (i = 0; i < 16; i++) {
- spiReceive(mmcp->mmc_spip, 1, buf);
+ spiReceiveWait(mmcp->mmc_spip, 1, buf);
if (buf[0] == 0xFF)
break;
}
/* Looks like it is a long wait.*/
while (TRUE) {
- spiReceive(mmcp->mmc_spip, 1, buf);
+ spiReceiveWait(mmcp->mmc_spip, 1, buf);
if (buf[0] == 0xFF)
break;
#ifdef MMC_NICE_WAITING
@@ -121,7 +121,7 @@ static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) {
buf[3] = arg >> 8;
buf[4] = arg;
buf[5] = 0x95; /* Valid for CMD0 ignored by other commands. */
- spiSend(mmcp->mmc_spip, 6, buf);
+ spiSendWait(mmcp->mmc_spip, 6, buf);
}
/**
@@ -138,7 +138,7 @@ static uint8_t recvr1(MMCDriver *mmcp) {
uint8_t r1[1];
for (i = 0; i < 9; i++) {
- spiReceive(mmcp->mmc_spip, 1, r1);
+ spiReceiveWait(mmcp->mmc_spip, 1, r1);
if (r1[0] != 0xFF)
return r1[0];
}
@@ -178,7 +178,7 @@ static void sync(MMCDriver *mmcp) {
spiSelect(mmcp->mmc_spip);
while (TRUE) {
- spiReceive(mmcp->mmc_spip, 1, buf);
+ spiReceiveWait(mmcp->mmc_spip, 1, buf);
if (buf[0] == 0xFF)
break;
#ifdef MMC_NICE_WAITING
@@ -306,7 +306,7 @@ bool_t mmcConnect(MMCDriver *mmcp) {
if (mmcp->mmc_state == MMC_INSERTED) {
/* Slow clock mode and 128 clock pulses.*/
spiStart(mmcp->mmc_spip, mmcp->mmc_lscfg);
- spiIgnore(mmcp->mmc_spip, 16);
+ spiSynchronizeWait(mmcp->mmc_spip, 16);
/* SPI mode selection.*/
i = 0;
@@ -453,11 +453,11 @@ bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
chSysUnlock();
for (i = 0; i < MMC_WAIT_DATA; i++) {
- spiReceive(mmcp->mmc_spip, 1, buffer);
+ spiReceiveWait(mmcp->mmc_spip, 1, buffer);
if (buffer[0] == 0xFE) {
- spiReceive(mmcp->mmc_spip, MMC_SECTOR_SIZE, buffer);
+ spiReceiveWait(mmcp->mmc_spip, MMC_SECTOR_SIZE, buffer);
/* CRC ignored. */
- spiIgnore(mmcp->mmc_spip, 2);
+ spiIgnoreWait(mmcp->mmc_spip, 2);
return FALSE;
}
}
@@ -493,7 +493,7 @@ bool_t mmcStopSequentialRead(MMCDriver *mmcp) {
}
chSysUnlock();
- spiSend(mmcp->mmc_spip, sizeof(stopcmd), stopcmd);
+ spiSendWait(mmcp->mmc_spip, sizeof(stopcmd), stopcmd);
/* result = recvr1(mmcp) != 0x00;*/
/* Note, ignored r1 response, it can be not zero, unknown issue.*/
recvr1(mmcp);
@@ -568,10 +568,10 @@ bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
}
chSysUnlock();
- spiSend(mmcp->mmc_spip, sizeof(start), start); /* Data prologue. */
- spiSend(mmcp->mmc_spip, MMC_SECTOR_SIZE, buffer); /* Data. */
- spiIgnore(mmcp->mmc_spip, 2); /* CRC ignored. */
- spiReceive(mmcp->mmc_spip, 1, b);
+ spiSendWait(mmcp->mmc_spip, sizeof(start), start); /* Data prologue. */
+ spiSendWait(mmcp->mmc_spip, MMC_SECTOR_SIZE, buffer); /* Data. */
+ spiIgnoreWait(mmcp->mmc_spip, 2); /* CRC ignored. */
+ spiReceiveWait(mmcp->mmc_spip, 1, b);
if ((b[0] & 0x1F) == 0x05) {
wait(mmcp);
return FALSE;
@@ -608,7 +608,7 @@ bool_t mmcStopSequentialWrite(MMCDriver *mmcp) {
}
chSysUnlock();
- spiSend(mmcp->mmc_spip, sizeof(stop), stop);
+ spiSendWait(mmcp->mmc_spip, sizeof(stop), stop);
spiUnselect(mmcp->mmc_spip);
chSysLock();
diff --git a/testhal/STM32/SPI/main.c b/testhal/STM32/SPI/main.c
index a8a8595f1..09e3131f9 100644
--- a/testhal/STM32/SPI/main.c
+++ b/testhal/STM32/SPI/main.c
@@ -24,6 +24,7 @@
* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig hs_spicfg = {
+ NULL,
GPIOA,
GPIOA_SPI1NSS,
0
@@ -33,6 +34,7 @@ static const SPIConfig hs_spicfg = {
* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig ls_spicfg = {
+ NULL,
GPIOA,
GPIOA_SPI1NSS,
SPI_CR1_BR_2 | SPI_CR1_BR_1
@@ -56,8 +58,8 @@ static msg_t spi_thread_1(void *p) {
palClearPad(IOPORT3, GPIOC_LED); /* LED ON. */
spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */
spiSelect(&SPID1); /* Slave Select assertion. */
- spiExchange(&SPID1, 512,
- txbuf, rxbuf); /* Atomic transfer operations. */
+ spiExchangeWait(&SPID1, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
spiUnselect(&SPID1); /* Slave Select de-assertion. */
spiReleaseBus(&SPID1); /* Ownership release. */
}
@@ -76,8 +78,8 @@ static msg_t spi_thread_2(void *p) {
palSetPad(IOPORT3, GPIOC_LED); /* LED OFF. */
spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */
spiSelect(&SPID1); /* Slave Select assertion. */
- spiExchange(&SPID1, 512,
- txbuf, rxbuf); /* Atomic transfer operations. */
+ spiExchangeWait(&SPID1, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
spiUnselect(&SPID1); /* Slave Select de-assertion. */
spiReleaseBus(&SPID1); /* Ownership release. */
}