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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 14:25:39 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 14:25:39 +0000 |
| commit | 8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e (patch) | |
| tree | ca94c78ac5bacf1740e95dd60d8e0f5288056bfe /testhal/SPC564Axx | |
| parent | 126943984c591c952bd0b9f6b2d36d97be823de3 (diff) | |
| download | ChibiOS-8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e.tar.gz ChibiOS-8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e.tar.bz2 ChibiOS-8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5849 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/SPC564Axx')
| -rw-r--r-- | testhal/SPC564Axx/SPI/mcuconf.h | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/testhal/SPC564Axx/SPI/mcuconf.h b/testhal/SPC564Axx/SPI/mcuconf.h index 0683912f9..2fccca076 100644 --- a/testhal/SPC564Axx/SPI/mcuconf.h +++ b/testhal/SPC564Axx/SPI/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC564Axx_MCUCONF
@@ -45,6 +47,25 @@ BIUCR_BFEN)
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* ADC driver settings.
*/
#define SPC5_ADC_USE_ADC0_Q0 FALSE
@@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE
#define SPC5_ADC_USE_ADC1_Q4 FALSE
#define SPC5_ADC_USE_ADC1_Q5 FALSE
-#define SPC5_ADC_FIFO0_DMA_PRIO 12
-#define SPC5_ADC_FIFO1_DMA_PRIO 12
-#define SPC5_ADC_FIFO2_DMA_PRIO 12
-#define SPC5_ADC_FIFO3_DMA_PRIO 12
-#define SPC5_ADC_FIFO4_DMA_PRIO 12
-#define SPC5_ADC_FIFO5_DMA_PRIO 12
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
@@ -115,9 +130,6 @@ SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO 10
-#define SPC5_SPI_DSPI2_DMA_PRIO 10
-#define SPC5_SPI_DSPI3_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
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