diff options
| -rw-r--r-- | demos/PPC-SPC560P-GCC/mcuconf.h | 91 | ||||
| -rw-r--r-- | demos/PPC-SPC563M-GCC/mcuconf.h | 4 | ||||
| -rw-r--r-- | demos/PPC-SPC564A-GCC/Makefile | 2 | ||||
| -rw-r--r-- | demos/PPC-SPC564A-GCC/mcuconf.h | 36 | ||||
| -rw-r--r-- | demos/PPC-SPC56EL-GCC/mcuconf.h | 150 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/spc560p_registry.h | 15 | ||||
| -rw-r--r-- | os/hal/platforms/SPC564Axx/spc564a_registry.h | 18 | ||||
| -rw-r--r-- | os/hal/platforms/SPC56ELxx/spc56el_registry.h | 9 | ||||
| -rw-r--r-- | testhal/SPC560Dxx/SPI/UDE/debug .wsx | 4 | ||||
| -rw-r--r-- | testhal/SPC560Dxx/SPI/main.c | 2 | ||||
| -rw-r--r-- | testhal/SPC560Pxx/PWM-ICU/mcuconf.h | 92 | ||||
| -rw-r--r-- | testhal/SPC560Pxx/SPI/mcuconf.h | 22 | ||||
| -rw-r--r-- | testhal/SPC563Mxx/ADC/mcuconf.h | 4 | ||||
| -rw-r--r-- | testhal/SPC563Mxx/SPI/mcuconf.h | 4 | ||||
| -rw-r--r-- | testhal/SPC564Axx/SPI/mcuconf.h | 30 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/PWM-ICU/mcuconf.h | 63 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/main.c | 2 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/mcuconf.h | 18 |
18 files changed, 485 insertions, 81 deletions
diff --git a/demos/PPC-SPC560P-GCC/mcuconf.h b/demos/PPC-SPC560P-GCC/mcuconf.h index f5e52b7f7..f30b63d8a 100644 --- a/demos/PPC-SPC560P-GCC/mcuconf.h +++ b/demos/PPC-SPC560P-GCC/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC560Pxx_MCUCONF
@@ -148,6 +150,15 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* SERIAL driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
@@ -162,3 +173,83 @@ SPC5_ME_PCTL_LP(2))
#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 TRUE
+#define SPC5_SPI_USE_DSPI1 TRUE
+#define SPC5_SPI_USE_DSPI2 TRUE
+#define SPC5_SPI_USE_DSPI3 TRUE
+#define SPC5_SPI_USE_DSPI4 FALSE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#define SPC5_SPI_DSPI3_IRQ_PRIO 10
+#define SPC5_SPI_DSPI4_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/demos/PPC-SPC563M-GCC/mcuconf.h b/demos/PPC-SPC563M-GCC/mcuconf.h index 28a5790f5..76898ad35 100644 --- a/demos/PPC-SPC563M-GCC/mcuconf.h +++ b/demos/PPC-SPC563M-GCC/mcuconf.h @@ -58,10 +58,6 @@ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
#define SPC5_EDMA_GROUP1_PRIORITIES \
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP2_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP3_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
diff --git a/demos/PPC-SPC564A-GCC/Makefile b/demos/PPC-SPC564A-GCC/Makefile index d79a29ab1..9b51a6845 100644 --- a/demos/PPC-SPC564A-GCC/Makefile +++ b/demos/PPC-SPC564A-GCC/Makefile @@ -59,7 +59,7 @@ include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk
# Define linker script file here
-LDSCRIPT= $(PORTLD)/SPC564A80.ld
+LDSCRIPT= $(PORTLD)/SPC564A70.ld
# C sources here.
CSRC = $(PORTSRC) \
diff --git a/demos/PPC-SPC564A-GCC/mcuconf.h b/demos/PPC-SPC564A-GCC/mcuconf.h index 0683912f9..dc54d3d88 100644 --- a/demos/PPC-SPC564A-GCC/mcuconf.h +++ b/demos/PPC-SPC564A-GCC/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC564Axx_MCUCONF
@@ -45,6 +47,25 @@ BIUCR_BFEN)
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* ADC driver settings.
*/
#define SPC5_ADC_USE_ADC0_Q0 FALSE
@@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE
#define SPC5_ADC_USE_ADC1_Q4 FALSE
#define SPC5_ADC_USE_ADC1_Q5 FALSE
-#define SPC5_ADC_FIFO0_DMA_PRIO 12
-#define SPC5_ADC_FIFO1_DMA_PRIO 12
-#define SPC5_ADC_FIFO2_DMA_PRIO 12
-#define SPC5_ADC_FIFO3_DMA_PRIO 12
-#define SPC5_ADC_FIFO4_DMA_PRIO 12
-#define SPC5_ADC_FIFO5_DMA_PRIO 12
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
@@ -88,9 +103,9 @@ /*
* SPI driver system settings.
*/
-#define SPC5_SPI_USE_DSPI1 TRUE
-#define SPC5_SPI_USE_DSPI2 TRUE
-#define SPC5_SPI_USE_DSPI3 TRUE
+#define SPC5_SPI_USE_DSPI1 FALSE
+#define SPC5_SPI_USE_DSPI2 FALSE
+#define SPC5_SPI_USE_DSPI3 FALSE
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
@@ -115,9 +130,6 @@ SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO 10
-#define SPC5_SPI_DSPI2_DMA_PRIO 10
-#define SPC5_SPI_DSPI3_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
diff --git a/demos/PPC-SPC56EL-GCC/mcuconf.h b/demos/PPC-SPC56EL-GCC/mcuconf.h index 96f8c6b86..f90a80578 100644 --- a/demos/PPC-SPC56EL-GCC/mcuconf.h +++ b/demos/PPC-SPC56EL-GCC/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC56ELxx_MCUCONF
@@ -41,9 +43,9 @@ #define SPC5_FMPLL1_IDF_VALUE 5
#define SPC5_FMPLL1_NDIV_VALUE 60
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
-#define SPC5_SYSCLK_DIVIDER_VALUE 1
+#define SPC5_SYSCLK_DIVIDER_VALUE 2
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
-#define SPC5_MCONTROL_DIVIDER_VALUE 2
+#define SPC5_MCONTROL_DIVIDER_VALUE 15
#define SPC5_SWG_DIVIDER_VALUE 2
#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1
#define SPC5_FLEXRAY_DIVIDER_VALUE 2
@@ -104,18 +106,6 @@ SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
-#define SPC5_ME_RUN_PC0_BITS 0
-#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \
- SPC5_ME_RUN_PC_DRUN | \
- SPC5_ME_RUN_PC_RUN0 | \
- SPC5_ME_RUN_PC_RUN1 | \
- SPC5_ME_RUN_PC_RUN2 | \
- SPC5_ME_RUN_PC_RUN3)
-#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
- SPC5_ME_RUN_PC_RUN0 | \
- SPC5_ME_RUN_PC_RUN1 | \
- SPC5_ME_RUN_PC_RUN2 | \
- SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
@@ -136,11 +126,6 @@ SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
-#define SPC5_ME_LP_PC0_BITS 0
-#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
- SPC5_ME_LP_PC_STOP0)
-#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
-#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
@@ -152,6 +137,15 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* SERIAL driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
@@ -166,3 +160,121 @@ SPC5_ME_PCTL_LP(2))
#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+
+/*
+ * PWM driver system settings.
+ */
+#define SPC5_PWM_USE_SMOD0 FALSE
+#define SPC5_PWM_USE_SMOD1 FALSE
+#define SPC5_PWM_USE_SMOD2 FALSE
+#define SPC5_PWM_USE_SMOD3 FALSE
+#define SPC5_PWM_SMOD0_PRIORITY 7
+#define SPC5_PWM_SMOD1_PRIORITY 7
+#define SPC5_PWM_SMOD2_PRIORITY 7
+#define SPC5_PWM_SMOD3_PRIORITY 7
+#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_PWM_USE_SMOD4 FALSE
+#define SPC5_PWM_USE_SMOD5 FALSE
+#define SPC5_PWM_USE_SMOD6 FALSE
+#define SPC5_PWM_USE_SMOD7 FALSE
+#define SPC5_PWM_SMOD4_PRIORITY 7
+#define SPC5_PWM_SMOD5_PRIORITY 7
+#define SPC5_PWM_SMOD6_PRIORITY 7
+#define SPC5_PWM_SMOD7_PRIORITY 7
+#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * ICU driver system settings.
+ */
+#define SPC5_ICU_USE_SMOD0 FALSE
+#define SPC5_ICU_USE_SMOD1 FALSE
+#define SPC5_ICU_USE_SMOD2 FALSE
+#define SPC5_ICU_USE_SMOD3 FALSE
+#define SPC5_ICU_USE_SMOD4 FALSE
+#define SPC5_ICU_USE_SMOD5 FALSE
+#define SPC5_ICU_ETIMER0_PRIORITY 7
+#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_SMOD6 FALSE
+#define SPC5_ICU_USE_SMOD7 FALSE
+#define SPC5_ICU_USE_SMOD8 FALSE
+#define SPC5_ICU_USE_SMOD9 FALSE
+#define SPC5_ICU_USE_SMOD10 FALSE
+#define SPC5_ICU_USE_SMOD11 FALSE
+#define SPC5_ICU_ETIMER1_PRIORITY 7
+#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_SMOD12 FALSE
+#define SPC5_ICU_USE_SMOD13 FALSE
+#define SPC5_ICU_USE_SMOD14 FALSE
+#define SPC5_ICU_USE_SMOD15 FALSE
+#define SPC5_ICU_USE_SMOD16 FALSE
+#define SPC5_ICU_USE_SMOD17 FALSE
+#define SPC5_ICU_ETIMER2_PRIORITY 7
+#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 FALSE
+#define SPC5_SPI_USE_DSPI1 FALSE
+#define SPC5_SPI_USE_DSPI2 FALSE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 54d38e0f6..4f528056e 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -93,6 +93,15 @@ #define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_DSPI2_RX_DMA_CH_ID 12
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
@@ -124,6 +133,9 @@ #if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_DSPI3 TRUE
#define SPC5_DSPI3_PCTL 7
+#define SPC5_DSPI3_TX1_DMA_CH_ID 13
+#define SPC5_DSPI3_TX2_DMA_CH_ID 14
+#define SPC5_DSPI3_RX_DMA_CH_ID 15
#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
#define SPC5_DSPI3_RX_DMA_DEV_ID 8
@@ -140,6 +152,9 @@ #if defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_DSPI4 TRUE
#define SPC5_DSPI4_PCTL 8
+#define SPC5_DSPI4_TX1_DMA_CH_ID 1
+#define SPC5_DSPI4_TX2_DMA_CH_ID 2
+#define SPC5_DSPI4_RX_DMA_CH_ID 3
#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
#define SPC5_DSPI4_RX_DMA_DEV_ID 21
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index bcdd6753b..ec584abdf 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -54,15 +54,15 @@ #define SPC5_HAS_DSPI3 TRUE
#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
-#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
-#define SPC5_DSPI1_TX2_DMA_DEV_ID 24
-#define SPC5_DSPI1_RX_DMA_DEV_ID 13
-#define SPC5_DSPI2_TX1_DMA_DEV_ID 14
-#define SPC5_DSPI2_TX2_DMA_DEV_ID 25
-#define SPC5_DSPI2_RX_DMA_DEV_ID 15
-#define SPC5_DSPI3_TX1_DMA_DEV_ID 16
-#define SPC5_DSPI3_TX2_DMA_DEV_ID 26
-#define SPC5_DSPI3_RX_DMA_DEV_ID 17
+#define SPC5_DSPI1_TX1_DMA_CH_ID 12
+#define SPC5_DSPI1_TX2_DMA_CH_ID 24
+#define SPC5_DSPI1_RX_DMA_CH_ID 13
+#define SPC5_DSPI2_TX1_DMA_CH_ID 14
+#define SPC5_DSPI2_TX2_DMA_CH_ID 25
+#define SPC5_DSPI2_RX_DMA_CH_ID 15
+#define SPC5_DSPI3_TX1_DMA_CH_ID 16
+#define SPC5_DSPI3_TX2_DMA_CH_ID 26
+#define SPC5_DSPI3_RX_DMA_CH_ID 17
#define SPC5_DSPI1_EOQF_HANDLER vector132
#define SPC5_DSPI1_EOQF_NUMBER 132
#define SPC5_DSPI1_TFFF_HANDLER vector133
diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h index 83fdab87c..6ab0ae2e2 100644 --- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -48,6 +48,15 @@ #define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_DSPI2_RX_DMA_CH_ID 12
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
diff --git a/testhal/SPC560Dxx/SPI/UDE/debug .wsx b/testhal/SPC560Dxx/SPI/UDE/debug .wsx index b85ffdc0a..8a1dc048c 100644 --- a/testhal/SPC560Dxx/SPI/UDE/debug .wsx +++ b/testhal/SPC560Dxx/SPI/UDE/debug .wsx @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="ISO-8859-1"?>
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Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData><ToolItemPersistData><Name>UDE_0x3B_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}</Name><Visible>true</Visible><Text>Run Macro</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x40_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}</Name><Visible>true</Visible><Text>Debug Macro</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x3_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}</Name><Visible>true</Visible><Text>Break Macro</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x3C_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}</Name><Visible>true</Visible><Text>Reload Macro</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Ctrl_{4D5190CD-077D-4F92-B890-4545242BF32A}_UDEWorkspace</Name><Visible>true</Visible><Text/><DisplayStyle>ImageAndText</DisplayStyle><AppendAccelerator>false</AppendAccelerator></ToolItemPersistData></ToolItemData></ToolbarPersistData><ToolbarPersistData><Bounds><X>375</X><Y>24</Y><Width>210</Width><Height>25</Height></Bounds><Name>File Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData><ToolItemPersistData><Name>UDE_Workspace_0x1770</Name><Visible>true</Visible><Text>New Workspace</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Workspace_0x1771</Name><Visible>true</Visible><Text>Open workspace</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Workspace_0x1772</Name><Visible>true</Visible><Text>Save workspace as</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Workspace_0x1773</Name><Visible>true</Visible><Text>Save workspace</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Workspace_0x1774</Name><Visible>true</Visible><Text>Close workspace</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Workspace_0x177F</Name><Visible>true</Visible><Text>Export view content</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Workspace_0x1778</Name><Visible>true</Visible><Text>Print</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x1_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Load Program</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData></ToolItemData></ToolbarPersistData><ToolbarPersistData><Bounds><X>585</X><Y>24</Y><Width>440</Width><Height>25</Height></Bounds><Name>Views Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData><ToolItemPersistData><Name>UDE_0x4_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}</Name><Visible>true</Visible><Text>Target Browser</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x15_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}</Name><Visible>true</Visible><Text>Diagnostic Message Viewer</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xF_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}</Name><Visible>true</Visible><Text>Console</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x0_{DED51A60-E0B7-11D4-9112-0001034962B6}</Name><Visible>true</Visible><Text>CPU Window</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x1E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Explore Symbols</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xA_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Program</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x5C_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Single Program Window</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x5A_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Disassembly Window</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x2D_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Show Special Function Register</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x3C_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Locals</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x46_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Watch</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xA_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Simulated I/O</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x14_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>UDE HTML</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x19_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Array Chart</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x1B_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Time Traced Signal Chart</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x50_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>IP Trace Profiling</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x28_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Memory</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x46_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Call Stack</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData></ToolItemData></ToolbarPersistData><ToolbarPersistData><Bounds><X>3</X><Y>49</Y><Width>509</Width><Height>25</Height></Bounds><Name>Debug Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData><ToolItemPersistData><Name>UDE_0x18_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Show IP</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x5E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}</Name><Visible>true</Visible><Text>Show program code</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x7_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Start Program</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x9_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Step Over</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xA_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Step Into</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xB_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Step Out</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x8_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Run Cursor</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x321_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Break Program</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xD_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Reset</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xC_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Restart Program</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x3_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Breakpoints</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x6_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}</Name><Visible>true</Visible><Text>Toggle Break</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_Core</Name><Visible>true</Visible><Text/><DisplayStyle>ImageAndText</DisplayStyle><AppendAccelerator>false</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x3_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}</Name><Visible>true</Visible><Text>Trigger setup</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData></ToolItemData></ToolbarPersistData><ToolbarPersistData><Bounds><X>512</X><Y>49</Y><Width>141</Width><Height>25</Height></Bounds><Name>Config Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData><ToolItemPersistData><Name>UDE_0x3_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}</Name><Visible>true</Visible><Text>Target Configuration</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xFE_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Connect Target</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x100_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Disconnect Target</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x6_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}</Name><Visible>true</Visible><Text>Setup Target Interface</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0x12_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}</Name><Visible>true</Visible><Text>MCU Run Control</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData></ToolItemData></ToolbarPersistData><ToolbarPersistData><Bounds><X>653</X><Y>49</Y><Width>151</Width><Height>25</Height></Bounds><Name>Tools Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData><ToolItemPersistData><Name>UDE_Ctrl_{377CE046-823C-4A05-8828-13C25D345D77}_Core</Name><Visible>true</Visible><Text/><DisplayStyle>ImageAndText</DisplayStyle><AppendAccelerator>false</AppendAccelerator></ToolItemPersistData><ToolItemPersistData><Name>UDE_0xE1_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}</Name><Visible>true</Visible><Text>Execution Time Setup</Text><DisplayStyle>Image</DisplayStyle><AppendAccelerator>true</AppendAccelerator></ToolItemPersistData></ToolItemData></ToolbarPersistData><ToolbarPersistData><Bounds><X>0</X><Y>100</Y><Width>26</Width><Height>25</Height></Bounds><Name>Show Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>false</Visible><ToolItemData/></ToolbarPersistData><ToolbarPersistData><Bounds><X>0</X><Y>200</Y><Width>26</Width><Height>25</Height></Bounds><Name>Window Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>false</Visible><ToolItemData/></ToolbarPersistData><ToolbarPersistData><Bounds><X>0</X><Y>225</Y><Width>26</Width><Height>25</Height></Bounds><Name>Workspace Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>false</Visible><ToolItemData/></ToolbarPersistData><ToolbarPersistData><Bounds><X>0</X><Y>275</Y><Width>26</Width><Height>25</Height></Bounds><Name>Help Toolbar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>false</Visible><ToolItemData/></ToolbarPersistData></ToolBars></TopContainer><BottomContainer><PanelBounds><X>0</X><Y>717</Y><Width>1279</Width><Height>23</Height></PanelBounds><ToolBars><ToolbarPersistData><Bounds><X>0</X><Y>0</Y><Width>1279</Width><Height>23</Height></Bounds><Name>Platform Status Bar</Name><AlwaysUnvisible>false</AlwaysUnvisible><Visible>true</Visible><ToolItemData/></ToolbarPersistData></ToolBars></BottomContainer><LeftContainer><PanelBounds><X>0</X><Y>74</Y><Width>0</Width><Height>643</Height></PanelBounds><ToolBars/></LeftContainer><RightContainer><PanelBounds><X>1279</X><Y>74</Y><Width>0</Width><Height>643</Height></PanelBounds><ToolBars/></RightContainer></ToolbarControlData></ToolbarControlData></NETPlacementRoot></MainFrame><INI_SECTION type="key"><Macro type="key"><MacroLib type="string">..\..\..\..\..\Program Files\pls\UDE 4.0\StdLibrary.mso</MacroLib></Macro><Loader type="key"><LOADER_REGKEY_WSP type="string">{866f82d3-fac5-43cd-8a82-0af01e46e2c5}</LOADER_REGKEY_WSP></Loader><PLACEMENT type="key"><SFRSelectDlg type="string">669,1006,350,661</SFRSelectDlg></PLACEMENT><EXTRAVALUE type="key"><SFRSelectDlg type="int">0</SFRSelectDlg></EXTRAVALUE></INI_SECTION><AddOns type="key"><UDE.Script type="key"><MacroGuiEntries type="key"><LastScriptFilePath type="string">..\..\..\..\..\Documents and Settings\disiriog\My Documents\pls\UDE 4.0</LastScriptFilePath><Macro_14_06_13_14_33_25_0 type="key"><ScriptDescription type="string">The script contains a collection of macros to save memory content into different file formats
and fill target memory ranges</ScriptDescription><ScriptPath type="string">V:\UDE\AddOns\Macro\MacroLibrary\StdMacros1.dsm</ScriptPath><ScriptSource type="string">'
' $Header: /Ude/AddOns/Macro/MacroLibrary/StdMacros.dsm 3 30.04.04 9:34 Weisses $
'_______________________________________________________
@@ -270,4 +270,4 @@ Sub FillDWord(ParameterObj) debugger.Write Address,udearrayobj
Next
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diff --git a/testhal/SPC560Dxx/SPI/main.c b/testhal/SPC560Dxx/SPI/main.c index 3aa7f2d7a..f6aa96abe 100644 --- a/testhal/SPC560Dxx/SPI/main.c +++ b/testhal/SPC560Dxx/SPI/main.c @@ -116,7 +116,7 @@ int main(void) { SIU.PCR[14].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
SIU.PCR[13].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
SIU.PCR[15].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */
- SIU.PCR[35].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[1] */
+ SIU.PCR[28].R = PAL_MODE_OUTPUT_ALTERNATE(3); /* CS[1] */
/* Testing sending and receiving at the same time.*/
spiExchange(&SPID1, 4, txbuf, rxbuf);
diff --git a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h index b396aece5..ae770ef86 100644 --- a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h +++ b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC560Pxx_MCUCONF
@@ -148,7 +150,16 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
- * PWM driver system settings.
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
+ * Serial driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
#define SPC5_SERIAL_USE_LINFLEX1 TRUE
@@ -206,3 +217,82 @@ #define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 FALSE
+#define SPC5_SPI_USE_DSPI1 FALSE
+#define SPC5_SPI_USE_DSPI2 FALSE
+#define SPC5_SPI_USE_DSPI3 FALSE
+#define SPC5_SPI_USE_DSPI4 FALSE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#define SPC5_SPI_DSPI3_IRQ_PRIO 10
+#define SPC5_SPI_DSPI4_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/testhal/SPC560Pxx/SPI/mcuconf.h b/testhal/SPC560Pxx/SPI/mcuconf.h index 940185854..ba5720366 100644 --- a/testhal/SPC560Pxx/SPI/mcuconf.h +++ b/testhal/SPC560Pxx/SPI/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC560Pxx_MCUCONF
@@ -148,7 +150,16 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
- * PWM driver system settings.
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
+ * Serial driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
#define SPC5_SERIAL_USE_LINFLEX1 TRUE
@@ -166,7 +177,7 @@ /*
* PWM driver system settings.
*/
-#define SPC5_PWM_USE_SMOD0 TRUE
+#define SPC5_PWM_USE_SMOD0 FALSE
#define SPC5_PWM_USE_SMOD1 FALSE
#define SPC5_PWM_USE_SMOD2 FALSE
#define SPC5_PWM_USE_SMOD3 FALSE
@@ -182,7 +193,7 @@ /*
* ICU driver system settings.
*/
-#define SPC5_ICU_USE_SMOD0 TRUE
+#define SPC5_ICU_USE_SMOD0 FALSE
#define SPC5_ICU_USE_SMOD1 FALSE
#define SPC5_ICU_USE_SMOD2 FALSE
#define SPC5_ICU_USE_SMOD3 FALSE
@@ -254,11 +265,6 @@ SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI0_DMA_PRIO 10
-#define SPC5_SPI_DSPI1_DMA_PRIO 10
-#define SPC5_SPI_DSPI2_DMA_PRIO 10
-#define SPC5_SPI_DSPI3_DMA_PRIO 10
-#define SPC5_SPI_DSPI4_DMA_PRIO 10
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h index db7cfabb1..18cc088ac 100644 --- a/testhal/SPC563Mxx/ADC/mcuconf.h +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -58,10 +58,6 @@ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
#define SPC5_EDMA_GROUP1_PRIORITIES \
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP2_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP3_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h index a06df4fdc..6affa7878 100644 --- a/testhal/SPC563Mxx/SPI/mcuconf.h +++ b/testhal/SPC563Mxx/SPI/mcuconf.h @@ -58,10 +58,6 @@ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
#define SPC5_EDMA_GROUP1_PRIORITIES \
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP2_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP3_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
diff --git a/testhal/SPC564Axx/SPI/mcuconf.h b/testhal/SPC564Axx/SPI/mcuconf.h index 0683912f9..2fccca076 100644 --- a/testhal/SPC564Axx/SPI/mcuconf.h +++ b/testhal/SPC564Axx/SPI/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC564Axx_MCUCONF
@@ -45,6 +47,25 @@ BIUCR_BFEN)
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* ADC driver settings.
*/
#define SPC5_ADC_USE_ADC0_Q0 FALSE
@@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE
#define SPC5_ADC_USE_ADC1_Q4 FALSE
#define SPC5_ADC_USE_ADC1_Q5 FALSE
-#define SPC5_ADC_FIFO0_DMA_PRIO 12
-#define SPC5_ADC_FIFO1_DMA_PRIO 12
-#define SPC5_ADC_FIFO2_DMA_PRIO 12
-#define SPC5_ADC_FIFO3_DMA_PRIO 12
-#define SPC5_ADC_FIFO4_DMA_PRIO 12
-#define SPC5_ADC_FIFO5_DMA_PRIO 12
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
@@ -115,9 +130,6 @@ SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO 10
-#define SPC5_SPI_DSPI2_DMA_PRIO 10
-#define SPC5_SPI_DSPI3_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
diff --git a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h index 435c18e86..221ad245e 100644 --- a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h +++ b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC56ELxx_MCUCONF
@@ -41,7 +43,7 @@ #define SPC5_FMPLL1_IDF_VALUE 5
#define SPC5_FMPLL1_NDIV_VALUE 60
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
-#define SPC5_SYSCLK_DIVIDER_VALUE 1
+#define SPC5_SYSCLK_DIVIDER_VALUE 2
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
#define SPC5_MCONTROL_DIVIDER_VALUE 15
#define SPC5_SWG_DIVIDER_VALUE 2
@@ -135,6 +137,15 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* SERIAL driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
@@ -217,3 +228,53 @@ SPC5_ME_PCTL_LP(2))
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 FALSE
+#define SPC5_SPI_USE_DSPI1 FALSE
+#define SPC5_SPI_USE_DSPI2 FALSE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/testhal/SPC56ELxx/SPI/main.c b/testhal/SPC56ELxx/SPI/main.c index cdabc06b9..ef283f656 100644 --- a/testhal/SPC56ELxx/SPI/main.c +++ b/testhal/SPC56ELxx/SPI/main.c @@ -30,7 +30,7 @@ static const SPIConfig hs_spicfg = { };
/*
- * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first).
+ * Low speed SPI configuration.
*/
static const SPIConfig ls_spicfg = {
NULL,
diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h index 384741bdd..322a9be56 100644 --- a/testhal/SPC56ELxx/SPI/mcuconf.h +++ b/testhal/SPC56ELxx/SPI/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC56ELxx_MCUCONF
@@ -135,6 +137,15 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING 0
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* SERIAL driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
@@ -153,7 +164,7 @@ /*
* PWM driver system settings.
*/
-#define SPC5_PWM_USE_SMOD0 TRUE
+#define SPC5_PWM_USE_SMOD0 FALSE
#define SPC5_PWM_USE_SMOD1 FALSE
#define SPC5_PWM_USE_SMOD2 FALSE
#define SPC5_PWM_USE_SMOD3 FALSE
@@ -182,7 +193,7 @@ /*
* ICU driver system settings.
*/
-#define SPC5_ICU_USE_SMOD0 TRUE
+#define SPC5_ICU_USE_SMOD0 FALSE
#define SPC5_ICU_USE_SMOD1 FALSE
#define SPC5_ICU_USE_SMOD2 FALSE
#define SPC5_ICU_USE_SMOD3 FALSE
@@ -248,9 +259,6 @@ SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI0_DMA_PRIO 10
-#define SPC5_SPI_DSPI1_DMA_PRIO 10
-#define SPC5_SPI_DSPI2_DMA_PRIO 10
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
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