STM32 FSMC NAND. Cleaned rest of v2.6 calls

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7130 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 17 insertions, 23 deletions

diff --git a/os/hal/ports/STM32/LLD/emc_lld.c b/os/hal/ports/STM32/LLD/emc_lld.c
index 2706fd8c3..885a12965 100644
--- a/os/hal/ports/STM32/LLD/emc_lld.c
+++ b/os/hal/ports/STM32/LLD/emc_lld.c
@@ -106,8 +106,7 @@ void emc_lld_start(EMCDriver *emcp) {
       rccResetFSMC();
       rccEnableFSMC(FALSE);
   #if STM32_EMC_USE_INT
-      nvicEnableVector(FSMC_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_EMC_FSMC1_IRQ_PRIORITY));
+      nvicEnableVector(FSMC_IRQn, STM32_EMC_FSMC1_IRQ_PRIORITY);
   #endif /* STM32_EMC_USE_INT */
     }
 #endif /* PLATFORM_STM32_USE_EMC1 */
@@ -150,9 +149,8 @@ void emc_lld_stop(EMCDriver *emcp) {
  * @notapi
  */
 void emc_lld_serve_interrupt(void) {
-#warning "This functionality untested"
 
-  chDbgPanic("Unrealized");
+  osalSysHalt("Unrealized");
 }
 
 /**
@@ -161,17 +159,19 @@ void emc_lld_serve_interrupt(void) {
  * @notapi
  */
 CH_IRQ_HANDLER(FSMC_IRQHandler) {
-#warning "This functionality untested"
+  osalSysHalt("This functionality untested");
 
   CH_IRQ_PROLOGUE();
-
+#if STM32_EMCNAND_USE_EMCNAND1
   if (EMCD1.nand1->SR & FSMC_SR_ISR_MASK){
     EMCNANDD1.isr_handler(&EMCNANDD1, EMCD1.nand1->SR);
   }
+#endif
+#if STM32_EMCNAND_USE_EMCNAND2
   if (EMCD1.nand2->SR & FSMC_SR_ISR_MASK){
     EMCNANDD2.isr_handler(&EMCNANDD2, EMCD1.nand2->SR);
   }
-
+#endif
   CH_IRQ_EPILOGUE();
 }
 #endif /* STM32_EMC_USE_INT */
diff --git a/os/hal/ports/STM32/LLD/emcnand_lld.c b/os/hal/ports/STM32/LLD/emcnand_lld.c
index a00ae7121..9ed6db9bd 100644
--- a/os/hal/ports/STM32/LLD/emcnand_lld.c
+++ b/os/hal/ports/STM32/LLD/emcnand_lld.c
@@ -74,16 +74,10 @@ EMCNANDDriver EMCNANDD2;
  *
  * @notapi
  */
-static void wakeup_isr(EMCNANDDriver *emcnandp, msg_t msg){
+static void wakeup_isr(EMCNANDDriver *emcnandp){
 
   osalDbgCheck(emcnandp->thread != NULL);
-
-  if (emcnandp->thread) {
-    thread_t *tp = emcnandp->thread;
-    emcnandp->thread = NULL;
-    tp->p_u.rdymsg = msg;
-    chSchReadyI(tp);
-  }
+  osalThreadResumeI(&emcnandp->thread, MSG_OK);
 }
 
 /**
@@ -93,8 +87,8 @@ static void wakeup_isr(EMCNANDDriver *emcnandp, msg_t msg){
  */
 static void emcnand_lld_suspend_thread(EMCNANDDriver *emcnandp) {
 
-  emcnandp->thread = chThdGetSelfX();
-  chSchGoSleepS(CH_STATE_SUSPENDED);
+  //emcnandp->thread = chThdGetSelfX();
+  osalThreadSuspendS(&emcnandp->thread);
 }
 
 /**
@@ -130,7 +124,7 @@ static uint32_t calc_eccps(EMCNANDDriver *emcnandp){
  */
 static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) {
   emcnandp->nand->SR |= FSMC_SR_IREN;
-  chDbgPanic("Function untested");
+  osalSysHalt("Function untested");
 }
 
 /**
@@ -142,7 +136,7 @@ static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) {
  */
 static void emcnand_ready_isr_disable(EMCNANDDriver *emcnandp) {
   emcnandp->nand->SR &= ~FSMC_SR_IREN;
-  chDbgPanic("Function untested");
+  osalSysHalt("Function untested");
 }
 
 /**
@@ -158,7 +152,7 @@ static void emcnand_isr_handler (EMCNANDDriver *emcnandp,
   (void)emcnandp;
   (void)flags;
 
-  chDbgPanic("Unrealized");
+  osalSysHalt("Unrealized");
 }
 #else /* STM32_EMC_USE_INT */
 /**
@@ -205,13 +199,13 @@ static void emcnand_isr_handler(EMCNANDDriver *emcnandp){
   case EMCNAND_ERASE:
     /* NAND reports about erase finish */
     emcnandp->state = EMCNAND_READY;
-    wakeup_isr(emcnandp, MSG_OK);
+    wakeup_isr(emcnandp);
     break;
 
   case EMCNAND_PROGRAM:
     /* NAND reports about page programming finish */
     emcnandp->state = EMCNAND_READY;
-    wakeup_isr(emcnandp, MSG_OK);
+    wakeup_isr(emcnandp);
     break;
 
   default:
@@ -257,7 +251,7 @@ static void emcnand_lld_serve_transfer_end_irq(EMCNANDDriver *emcnandp,
     emcnandp->state = EMCNAND_READY;
     emcnandp->rxdata = NULL;
     emcnandp->datalen = 0;
-    wakeup_isr(emcnandp, MSG_OK);
+    wakeup_isr(emcnandp);
     break;
 
   default: