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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-21 18:49:04 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-21 18:49:04 +0000 |
| commit | 334c7d645d1eccc59b9e19678b5e47d1e3ae2320 (patch) | |
| tree | 7d10743985bd29c48c818f872f4fd7365fe19d96 /os/ports/common/ARMCMx/CMSIS | |
| parent | 6100dc08a6a9f4592f324204bad26ba11239a030 (diff) | |
| download | ChibiOS-334c7d645d1eccc59b9e19678b5e47d1e3ae2320.tar.gz ChibiOS-334c7d645d1eccc59b9e19678b5e47d1e3ae2320.tar.bz2 ChibiOS-334c7d645d1eccc59b9e19678b5e47d1e3ae2320.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3645 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports/common/ARMCMx/CMSIS')
| -rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cm3.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h index c15e10ae2..0ced2caa5 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h @@ -1,8 +1,8 @@ /**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V2.10
- * @date 19. July 2011
+ * @version V2.11
+ * @date 08. September 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
@@ -97,8 +97,8 @@ #endif
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED 0
+
+#define __FPU_USED 0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
@@ -376,8 +376,16 @@ typedef struct #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|