git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3645 35acf78f-673a-0410-8e92-d51de3d6d3f4

19 files changed, 129 insertions, 659 deletions

diff --git a/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/os/ports/GCC/ARMCMx/LPC11xx/port.mk
index 1b9c8cf9f..8bfd25ad3 100644
--- a/os/ports/GCC/ARMCMx/LPC11xx/port.mk
+++ b/os/ports/GCC/ARMCMx/LPC11xx/port.mk
@@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
           $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \

-          ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c

+          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c

 

 PORTASM =

 

 PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \

+          ${CHIBIOS}/os/ports/common/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx

 

diff --git a/os/ports/GCC/ARMCMx/LPC13xx/port.mk b/os/ports/GCC/ARMCMx/LPC13xx/port.mk
index d7037a6ea..fa392c5d5 100644
--- a/os/ports/GCC/ARMCMx/LPC13xx/port.mk
+++ b/os/ports/GCC/ARMCMx/LPC13xx/port.mk
@@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
           $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \

-          ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c

+          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c

 

 PORTASM =

 

 PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \

+          ${CHIBIOS}/os/ports/common/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx

 

diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/port.mk b/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
index fed431182..1ba6c672e 100644
--- a/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
+++ b/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
@@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
           $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \

-          ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c

+          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c

 

 PORTASM =

 

 PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \

+          ${CHIBIOS}/os/ports/common/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx

 

diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
index 072e2d363..0211cb3b8 100644
--- a/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+++ b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
@@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
           $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \

-          ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c

+          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c

 

 PORTASM =

 

 PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \

+          ${CHIBIOS}/os/ports/common/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx

 

diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/port.mk b/os/ports/GCC/ARMCMx/STM32L1xx/port.mk
index 4ed269619..93b177563 100644
--- a/os/ports/GCC/ARMCMx/STM32L1xx/port.mk
+++ b/os/ports/GCC/ARMCMx/STM32L1xx/port.mk
@@ -3,11 +3,12 @@ PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
           $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \

-          ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c

+          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c

 

 PORTASM =

 

 PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \

+          ${CHIBIOS}/os/ports/common/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx \

           ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx

 

diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h
index 16703ddcc..280b987e9 100644
--- a/os/ports/GCC/ARMCMx/chcore.h
+++ b/os/ports/GCC/ARMCMx/chcore.h
@@ -143,17 +143,6 @@
 #error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"

 #endif

 

-/**

- * @brief   Stack alignment enforcement.

- * @note    The default value is 64 in order to comply with EABI, reducing

- *          the value to 32 can save some RAM space if you don't care about

- *          binary compatibility with EABI compiled libraries.

- * @note    Allowed values are 32 or 64.

- */

-#if !defined(CORTEX_STACK_ALIGNMENT)

-#define CORTEX_STACK_ALIGNMENT          64

-#endif

-

 /*===========================================================================*/

 /* Port derived parameters (common).                                         */

 /*===========================================================================*/

@@ -189,19 +178,16 @@
 

 /**

  * @brief   Stack and memory alignment enforcement.

+ * @note    In this architecture the stack alignment is enforced to 64 bits,

+ *          32 bits alignment is supported by hardware but deprecated by ARM,

+ *          the implementation choice is to not offer the option.

  */

-#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__)

 #if defined(__DOXYGEN__)

 /* Dummy declaration, for Doxygen only.*/

 typedef uint64_t stkalign_t;

 #else

 typedef uint64_t stkalign_t __attribute__ ((aligned (8)));

 #endif

-#elif CORTEX_STACK_ALIGNMENT == 32

-typedef uint32_t stkalign_t __attribute__ ((aligned (4)));

-#else

-#error "invalid stack alignment selected"

-#endif

 

 #if defined(__DOXYGEN__)

 /**

diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h
index 71fffdac8..88c1cb28b 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.h
@@ -161,9 +161,9 @@ struct intctx {
  */

 #define port_init() {                                                       \

   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

-  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

 

diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c
index ca45f4f1a..437492c90 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v7m.c
@@ -28,17 +28,9 @@
 

 #include "ch.h"

 

-#if !CH_OPTIMIZE_SPEED

-void _port_lock(void) {

-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;

-  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");

-}

-

-void _port_unlock(void) {

-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;

-  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");

-}

-#endif

+/*===========================================================================*/

+/* Port interrupt handlers.                                                  */

+/*===========================================================================*/

 

 /**

  * @brief   System Timer vector.

@@ -109,6 +101,10 @@ void PendSVVector(void) {
 }

 #endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

+/*===========================================================================*/

+/* Port exported functions.                                                  */

+/*===========================================================================*/

+

 /**

  * @brief   Port-related initialization code.

  */

@@ -141,20 +137,30 @@ void _port_init(void) {
 #endif

 

   /* Initialization of the system vectors used by the port.*/

-  NVICSetSystemHandlerPriority(HANDLER_SVCALL,

+  nvicSetSystemHandlerPriority(HANDLER_SVCALL,

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));

-  NVICSetSystemHandlerPriority(HANDLER_PENDSV,

+  nvicSetSystemHandlerPriority(HANDLER_PENDSV,

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));

-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));

 }

+

+#if !CH_OPTIMIZE_SPEED

+void _port_lock(void) {

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;

+  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");

+}

+

+void _port_unlock(void) {

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;

+  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");

+}

+#endif

+

 /**

  * @brief   Exception exit redirection to _port_switch_from_isr().

  */

 void _port_irq_epilogue(void) {

-#if CORTEX_USE_FPU

-  uint32_t fpccr;

-#endif

 

   port_lock_from_isr();

   if ((SCB_ICSR & ICSR_RETTOBASE)) {

@@ -187,14 +193,17 @@ void _port_irq_epilogue(void) {
     }

 

 #if CORTEX_USE_FPU

-    /* Saving the special register SCB_FPCCR into the reserved offset of

-       the Cortex-M4 exception frame.*/

-    (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);

-#endif

-#if CORTEX_USE_FPU

-    /* Now the FPCCR is modified in order to not restore the FPU status

-       from the artificial return context.*/

-    SCB_FPCCR = fpccr | FPCCR_LSPACT;

+    {

+      uint32_t fpccr;

+

+      /* Saving the special register SCB_FPCCR into the reserved offset of

+         the Cortex-M4 exception frame.*/

+      (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);

+

+      /* Now the FPCCR is modified in order to not restore the FPU status

+         from the artificial return context.*/

+      SCB_FPCCR = fpccr | FPCCR_LSPACT;

+    }

 #endif

 

     /* Note, returning without unlocking is intentional, this is done in

diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h
index a7e59e8fd..9c7f77203 100644
--- a/os/ports/IAR/ARMCMx/chcore_v6m.h
+++ b/os/ports/IAR/ARMCMx/chcore_v6m.h
@@ -159,9 +159,9 @@ struct intctx {
  */

 #define port_init() {                                                       \

   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

-  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

 

diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h
index 8ebd45bda..38f77b7eb 100644
--- a/os/ports/IAR/ARMCMx/chcore_v7m.h
+++ b/os/ports/IAR/ARMCMx/chcore_v7m.h
@@ -201,11 +201,11 @@ struct intctx {
 #define port_init() {                                                       \

   SCB_VTOR = CORTEX_VTOR_INIT;                                              \

   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

-  NVICSetSystemHandlerPriority(HANDLER_SVCALL,                              \

+  nvicSetSystemHandlerPriority(HANDLER_SVCALL,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));                          \

-  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

 

diff --git a/os/ports/IAR/ARMCMx/nvic.c b/os/ports/IAR/ARMCMx/nvic.c
deleted file mode 100644
index 690c4e488..000000000
--- a/os/ports/IAR/ARMCMx/nvic.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*

-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

-                 2011 Giovanni Di Sirio.

-

-    This file is part of ChibiOS/RT.

-

-    ChibiOS/RT is free software; you can redistribute it and/or modify

-    it under the terms of the GNU General Public License as published by

-    the Free Software Foundation; either version 3 of the License, or

-    (at your option) any later version.

-

-    ChibiOS/RT is distributed in the hope that it will be useful,

-    but WITHOUT ANY WARRANTY; without even the implied warranty of

-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

-    GNU General Public License for more details.

-

-    You should have received a copy of the GNU General Public License

-    along with this program.  If not, see <http://www.gnu.org/licenses/>.

-*/

-

-/**

- * @file    IAR/ARMCMx/nvic.c

- * @brief   Cortex-Mx NVIC support code.

- *

- * @addtogroup IAR_ARMCMx_NVIC

- * @{

- */

-

-#include "ch.h"

-#include "nvic.h"

-

-/**

- * @brief Sets the priority of an interrupt handler and enables it.

- *

- * @param n the interrupt number

- * @param prio the interrupt priority mask

- *

- * @note The parameters are not tested for correctness.

- */

-void NVICEnableVector(uint32_t n, uint32_t prio) {

-  unsigned sh = (n & 3) << 3;

-

-  NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);

-  NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);

-  NVIC_ISER(n >> 5) = 1 << (n & 0x1F);

-}

-

-/**

- * @brief Disables an interrupt handler.

- *

- * @param n the interrupt number

- *

- * @note The parameters are not tested for correctness.

- */

-void NVICDisableVector(uint32_t n) {

-  unsigned sh = (n & 3) << 3;

-

-  NVIC_ICER(n >> 5) = 1 << (n & 0x1F);

-  NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);

-}

-

-/**

- * @brief Changes the priority of a system handler.

- *

- * @param handler the system handler number

- * @param prio the system handler priority mask

- * @note The parameters are not tested for correctness.

- */

-void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {

-  unsigned sh = (handler & 3) * 8;

-

-  SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &

-                           ~(0xFF << sh)) | (prio << sh);

-}

-

-/** @} */

diff --git a/os/ports/IAR/ARMCMx/nvic.h b/os/ports/IAR/ARMCMx/nvic.h
deleted file mode 100644
index f424a854d..000000000
--- a/os/ports/IAR/ARMCMx/nvic.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*

-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

-                 2011 Giovanni Di Sirio.

-

-    This file is part of ChibiOS/RT.

-

-    ChibiOS/RT is free software; you can redistribute it and/or modify

-    it under the terms of the GNU General Public License as published by

-    the Free Software Foundation; either version 3 of the License, or

-    (at your option) any later version.

-

-    ChibiOS/RT is distributed in the hope that it will be useful,

-    but WITHOUT ANY WARRANTY; without even the implied warranty of

-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

-    GNU General Public License for more details.

-

-    You should have received a copy of the GNU General Public License

-    along with this program.  If not, see <http://www.gnu.org/licenses/>.

-*/

-

-/**

- * @file    IAR/ARMCMx/nvic.h

- * @brief   Cortex-Mx NVIC support macros and structures.

- *

- * @addtogroup IAR_ARMCMx_NVIC

- * @{

- */

-

-#ifndef _NVIC_H_

-#define _NVIC_H_

-

-/*

- * System vector constants for @p NVICSetSystemHandlerPriority().

- */

-#define HANDLER_MEM_MANAGE      0       /**< MEM MANAGE vector id.          */

-#define HANDLER_BUS_FAULT       1       /**< BUS FAULT vector id.           */

-#define HANDLER_USAGE_FAULT     2       /**< USAGE FAULT vector id.         */

-#define HANDLER_RESERVED_3      3

-#define HANDLER_RESERVED_4      4

-#define HANDLER_RESERVED_5      5

-#define HANDLER_RESERVED_6      6

-#define HANDLER_SVCALL          7       /**< SVCALL vector id.              */

-#define HANDLER_DEBUG_MONITOR   8       /**< DEBUG MONITOR vector id.       */

-#define HANDLER_RESERVED_9      9

-#define HANDLER_PENDSV          10      /**< PENDSV vector id.              */

-#define HANDLER_SYSTICK         11      /**< SYS TCK vector id.             */

-

-typedef volatile uint8_t IOREG8;        /**< 8 bits I/O register type.      */

-typedef volatile uint32_t IOREG32;      /**< 32 bits I/O register type.     */

-

-/**

- * @brief NVIC ITCR register.

- */

-#define NVIC_ITCR               (*((IOREG32 *)0xE000E004))

-

-/**

- * @brief NVIC STIR register.

- */

-#define NVIC_STIR               (*((IOREG32 *)0xE000EF00))

-

-/**

- * @brief Structure representing the SYSTICK I/O space.

- */

-typedef struct {

-  IOREG32       CSR;

-  IOREG32       RVR;

-  IOREG32       CVR;

-  IOREG32       CBVR;

-} CM3_ST;

-

-/**

- * @brief SYSTICK peripheral base address.

- */

-#define STBase                  ((CM3_ST *)0xE000E010)

-#define ST_CSR                  (STBase->CSR)

-#define ST_RVR                  (STBase->RVR)

-#define ST_CVR                  (STBase->CVR)

-#define ST_CBVR                 (STBase->CBVR)

-

-#define CSR_ENABLE_MASK         (0x1 << 0)

-#define ENABLE_OFF_BITS         (0 << 0)

-#define ENABLE_ON_BITS          (1 << 0)

-#define CSR_TICKINT_MASK        (0x1 << 1)

-#define   TICKINT_DISABLED_BITS (0 << 1)

-#define   TICKINT_ENABLED_BITS  (1 << 1)

-#define CSR_CLKSOURCE_MASK      (0x1 << 2)

-#define   CLKSOURCE_EXT_BITS    (0 << 2)

-#define   CLKSOURCE_CORE_BITS   (1 << 2)

-#define CSR_COUNTFLAG_MASK      (0x1 << 16)

-

-#define RVR_RELOAD_MASK         (0xFFFFFF << 0)

-

-#define CVR_CURRENT_MASK        (0xFFFFFF << 0)

-

-#define CBVR_TENMS_MASK         (0xFFFFFF << 0)

-#define CBVR_SKEW_MASK          (0x1 << 30)

-#define CBVR_NOREF_MASK         (0x1 << 31)

-

-/**

- * @brief Structure representing the NVIC I/O space.

- */

-typedef struct {

-  IOREG32       ISER[8];

-  IOREG32       unused1[24];

-  IOREG32       ICER[8];

-  IOREG32       unused2[24];

-  IOREG32       ISPR[8];

-  IOREG32       unused3[24];

-  IOREG32       ICPR[8];

-  IOREG32       unused4[24];

-  IOREG32       IABR[8];

-  IOREG32       unused5[56];

-  IOREG32       IPR[60];

-} CM3_NVIC;

-

-/**

- * @brief NVIC peripheral base address.

- */

-#define NVICBase                ((CM3_NVIC *)0xE000E100)

-#define NVIC_ISER(n)            (NVICBase->ISER[n])

-#define NVIC_ICER(n)            (NVICBase->ICER[n])

-#define NVIC_ISPR(n)            (NVICBase->ISPR[n])

-#define NVIC_ICPR(n)            (NVICBase->ICPR[n])

-#define NVIC_IABR(n)            (NVICBase->IABR[n])

-#define NVIC_IPR(n)             (NVICBase->IPR[n])

-

-/**

- * @brief Structure representing the System Control Block I/O space.

- */

-typedef struct {

-  IOREG32       CPUID;

-  IOREG32       ICSR;

-  IOREG32       VTOR;

-  IOREG32       AIRCR;

-  IOREG32       SCR;

-  IOREG32       CCR;

-  IOREG32       SHPR[3];

-  IOREG32       SHCSR;

-  IOREG32       CFSR;

-  IOREG32       HFSR;

-  IOREG32       DFSR;

-  IOREG32       MMFAR;

-  IOREG32       BFAR;

-  IOREG32       AFSR;

-} CM3_SCB;

-

-/**

- * @brief SCB peripheral base address.

- */

-#define SCBBase                 ((CM3_SCB *)0xE000ED00)

-#define SCB_CPUID               (SCBBase->CPUID)

-#define SCB_ICSR                (SCBBase->ICSR)

-#define SCB_VTOR                (SCBBase->VTOR)

-#define SCB_AIRCR               (SCBBase->AIRCR)

-#define SCB_SCR                 (SCBBase->SCR)

-#define SCB_CCR                 (SCBBase->CCR)

-#define SCB_SHPR(n)             (SCBBase->SHPR[n])

-#define SCB_SHCSR               (SCBBase->SHCSR)

-#define SCB_CFSR                (SCBBase->CFSR)

-#define SCB_HFSR                (SCBBase->HFSR)

-#define SCB_DFSR                (SCBBase->DFSR)

-#define SCB_MMFAR               (SCBBase->MMFAR)

-#define SCB_BFAR                (SCBBase->BFAR)

-#define SCB_AFSR                (SCBBase->AFSR)

-

-#define ICSR_VECTACTIVE_MASK    (0x1FF << 0)

-#define ICSR_RETTOBASE          (0x1 << 11)

-#define ICSR_VECTPENDING_MASK   (0x1FF << 12)

-#define ICSR_ISRPENDING         (0x1 << 22)

-#define ICSR_ISRPREEMPT         (0x1 << 23)

-#define ICSR_PENDSTCLR          (0x1 << 25)

-#define ICSR_PENDSTSET          (0x1 << 26)

-#define ICSR_PENDSVCLR          (0x1 << 27)

-#define ICSR_PENDSVSET          (0x1 << 28)

-#define ICSR_NMIPENDSET         (0x1 << 31)

-

-#define AIRCR_VECTKEY           0x05FA0000

-#define AIRCR_PRIGROUP_MASK     (0x7 << 8)

-#define AIRCR_PRIGROUP(n)       ((n) << 8)

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-  void NVICEnableVector(uint32_t n, uint32_t prio);

-  void NVICDisableVector(uint32_t n);

-  void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* _NVIC_H_ */

-

-/** @} */

diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h
index a2598f03a..be8b7267b 100644
--- a/os/ports/RVCT/ARMCMx/chcore_v6m.h
+++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h
@@ -159,9 +159,9 @@ struct intctx {
  */

 #define port_init() {                                                       \

   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

-  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

 

diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h
index b4181d517..5a7b6eb0e 100644
--- a/os/ports/RVCT/ARMCMx/chcore_v7m.h
+++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h
@@ -201,11 +201,11 @@ struct intctx {
 #define port_init() {                                                       \

   SCB_VTOR = CORTEX_VTOR_INIT;                                              \

   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

-  NVICSetSystemHandlerPriority(HANDLER_SVCALL,                              \

+  nvicSetSystemHandlerPriority(HANDLER_SVCALL,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));                          \

-  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

 

diff --git a/os/ports/RVCT/ARMCMx/nvic.c b/os/ports/RVCT/ARMCMx/nvic.c
deleted file mode 100644
index 8656a288c..000000000
--- a/os/ports/RVCT/ARMCMx/nvic.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*

-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

-                 2011 Giovanni Di Sirio.

-

-    This file is part of ChibiOS/RT.

-

-    ChibiOS/RT is free software; you can redistribute it and/or modify

-    it under the terms of the GNU General Public License as published by

-    the Free Software Foundation; either version 3 of the License, or

-    (at your option) any later version.

-

-    ChibiOS/RT is distributed in the hope that it will be useful,

-    but WITHOUT ANY WARRANTY; without even the implied warranty of

-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

-    GNU General Public License for more details.

-

-    You should have received a copy of the GNU General Public License

-    along with this program.  If not, see <http://www.gnu.org/licenses/>.

-*/

-

-/**

- * @file    RVCT/ARMCMx/nvic.c

- * @brief   Cortex-Mx NVIC support code.

- *

- * @addtogroup RVCT_ARMCMx_NVIC

- * @{

- */

-

-#include "ch.h"

-#include "nvic.h"

-

-/**

- * @brief Sets the priority of an interrupt handler and enables it.

- *

- * @param n the interrupt number

- * @param prio the interrupt priority mask

- *

- * @note The parameters are not tested for correctness.

- */

-void NVICEnableVector(uint32_t n, uint32_t prio) {

-  unsigned sh = (n & 3) << 3;

-

-  NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);

-  NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);

-  NVIC_ISER(n >> 5) = 1 << (n & 0x1F);

-}

-

-/**

- * @brief Disables an interrupt handler.

- *

- * @param n the interrupt number

- *

- * @note The parameters are not tested for correctness.

- */

-void NVICDisableVector(uint32_t n) {

-  unsigned sh = (n & 3) << 3;

-

-  NVIC_ICER(n >> 5) = 1 << (n & 0x1F);

-  NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);

-}

-

-/**

- * @brief Changes the priority of a system handler.

- *

- * @param handler the system handler number

- * @param prio the system handler priority mask

- * @note The parameters are not tested for correctness.

- */

-void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {

-  unsigned sh = (handler & 3) * 8;

-

-  SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &

-                           ~(0xFF << sh)) | (prio << sh);

-}

-

-/** @} */

diff --git a/os/ports/RVCT/ARMCMx/nvic.h b/os/ports/RVCT/ARMCMx/nvic.h
deleted file mode 100644
index a1fbe4ea5..000000000
--- a/os/ports/RVCT/ARMCMx/nvic.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*

-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

-                 2011 Giovanni Di Sirio.

-

-    This file is part of ChibiOS/RT.

-

-    ChibiOS/RT is free software; you can redistribute it and/or modify

-    it under the terms of the GNU General Public License as published by

-    the Free Software Foundation; either version 3 of the License, or

-    (at your option) any later version.

-

-    ChibiOS/RT is distributed in the hope that it will be useful,

-    but WITHOUT ANY WARRANTY; without even the implied warranty of

-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

-    GNU General Public License for more details.

-

-    You should have received a copy of the GNU General Public License

-    along with this program.  If not, see <http://www.gnu.org/licenses/>.

-*/

-

-/**

- * @file    RVCT/ARMCMx/nvic.h

- * @brief   Cortex-Mx NVIC support macros and structures.

- *

- * @addtogroup RVCT_ARMCMx_NVIC

- * @{

- */

-

-#ifndef _NVIC_H_

-#define _NVIC_H_

-

-/*

- * System vector constants for @p NVICSetSystemHandlerPriority().

- */

-#define HANDLER_MEM_MANAGE      0       /**< MEM MANAGE vector id.          */

-#define HANDLER_BUS_FAULT       1       /**< BUS FAULT vector id.           */

-#define HANDLER_USAGE_FAULT     2       /**< USAGE FAULT vector id.         */

-#define HANDLER_RESERVED_3      3

-#define HANDLER_RESERVED_4      4

-#define HANDLER_RESERVED_5      5

-#define HANDLER_RESERVED_6      6

-#define HANDLER_SVCALL          7       /**< SVCALL vector id.              */

-#define HANDLER_DEBUG_MONITOR   8       /**< DEBUG MONITOR vector id.       */

-#define HANDLER_RESERVED_9      9

-#define HANDLER_PENDSV          10      /**< PENDSV vector id.              */

-#define HANDLER_SYSTICK         11      /**< SYS TCK vector id.             */

-

-typedef volatile uint8_t IOREG8;        /**< 8 bits I/O register type.      */

-typedef volatile uint32_t IOREG32;      /**< 32 bits I/O register type.     */

-

-/**

- * @brief NVIC ITCR register.

- */

-#define NVIC_ITCR               (*((IOREG32 *)0xE000E004))

-

-/**

- * @brief NVIC STIR register.

- */

-#define NVIC_STIR               (*((IOREG32 *)0xE000EF00))

-

-/**

- * @brief Structure representing the SYSTICK I/O space.

- */

-typedef struct {

-  IOREG32       CSR;

-  IOREG32       RVR;

-  IOREG32       CVR;

-  IOREG32       CBVR;

-} CM3_ST;

-

-/**

- * @brief SYSTICK peripheral base address.

- */

-#define STBase                  ((CM3_ST *)0xE000E010)

-#define ST_CSR                  (STBase->CSR)

-#define ST_RVR                  (STBase->RVR)

-#define ST_CVR                  (STBase->CVR)

-#define ST_CBVR                 (STBase->CBVR)

-

-#define CSR_ENABLE_MASK         (0x1 << 0)

-#define ENABLE_OFF_BITS         (0 << 0)

-#define ENABLE_ON_BITS          (1 << 0)

-#define CSR_TICKINT_MASK        (0x1 << 1)

-#define   TICKINT_DISABLED_BITS (0 << 1)

-#define   TICKINT_ENABLED_BITS  (1 << 1)

-#define CSR_CLKSOURCE_MASK      (0x1 << 2)

-#define   CLKSOURCE_EXT_BITS    (0 << 2)

-#define   CLKSOURCE_CORE_BITS   (1 << 2)

-#define CSR_COUNTFLAG_MASK      (0x1 << 16)

-

-#define RVR_RELOAD_MASK         (0xFFFFFF << 0)

-

-#define CVR_CURRENT_MASK        (0xFFFFFF << 0)

-

-#define CBVR_TENMS_MASK         (0xFFFFFF << 0)

-#define CBVR_SKEW_MASK          (0x1 << 30)

-#define CBVR_NOREF_MASK         (0x1 << 31)

-

-/**

- * @brief Structure representing the NVIC I/O space.

- */

-typedef struct {

-  IOREG32       ISER[8];

-  IOREG32       unused1[24];

-  IOREG32       ICER[8];

-  IOREG32       unused2[24];

-  IOREG32       ISPR[8];

-  IOREG32       unused3[24];

-  IOREG32       ICPR[8];

-  IOREG32       unused4[24];

-  IOREG32       IABR[8];

-  IOREG32       unused5[56];

-  IOREG32       IPR[60];

-} CM3_NVIC;

-

-/**

- * @brief NVIC peripheral base address.

- */

-#define NVICBase                ((CM3_NVIC *)0xE000E100)

-#define NVIC_ISER(n)            (NVICBase->ISER[n])

-#define NVIC_ICER(n)            (NVICBase->ICER[n])

-#define NVIC_ISPR(n)            (NVICBase->ISPR[n])

-#define NVIC_ICPR(n)            (NVICBase->ICPR[n])

-#define NVIC_IABR(n)            (NVICBase->IABR[n])

-#define NVIC_IPR(n)             (NVICBase->IPR[n])

-

-/**

- * @brief Structure representing the System Control Block I/O space.

- */

-typedef struct {

-  IOREG32       CPUID;

-  IOREG32       ICSR;

-  IOREG32       VTOR;

-  IOREG32       AIRCR;

-  IOREG32       SCR;

-  IOREG32       CCR;

-  IOREG32       SHPR[3];

-  IOREG32       SHCSR;

-  IOREG32       CFSR;

-  IOREG32       HFSR;

-  IOREG32       DFSR;

-  IOREG32       MMFAR;

-  IOREG32       BFAR;

-  IOREG32       AFSR;

-} CM3_SCB;

-

-/**

- * @brief SCB peripheral base address.

- */

-#define SCBBase                 ((CM3_SCB *)0xE000ED00)

-#define SCB_CPUID               (SCBBase->CPUID)

-#define SCB_ICSR                (SCBBase->ICSR)

-#define SCB_VTOR                (SCBBase->VTOR)

-#define SCB_AIRCR               (SCBBase->AIRCR)

-#define SCB_SCR                 (SCBBase->SCR)

-#define SCB_CCR                 (SCBBase->CCR)

-#define SCB_SHPR(n)             (SCBBase->SHPR[n])

-#define SCB_SHCSR               (SCBBase->SHCSR)

-#define SCB_CFSR                (SCBBase->CFSR)

-#define SCB_HFSR                (SCBBase->HFSR)

-#define SCB_DFSR                (SCBBase->DFSR)

-#define SCB_MMFAR               (SCBBase->MMFAR)

-#define SCB_BFAR                (SCBBase->BFAR)

-#define SCB_AFSR                (SCBBase->AFSR)

-

-#define ICSR_VECTACTIVE_MASK    (0x1FF << 0)

-#define ICSR_RETTOBASE          (0x1 << 11)

-#define ICSR_VECTPENDING_MASK   (0x1FF << 12)

-#define ICSR_ISRPENDING         (0x1 << 22)

-#define ICSR_ISRPREEMPT         (0x1 << 23)

-#define ICSR_PENDSTCLR          (0x1 << 25)

-#define ICSR_PENDSTSET          (0x1 << 26)

-#define ICSR_PENDSVCLR          (0x1 << 27)

-#define ICSR_PENDSVSET          (0x1 << 28)

-#define ICSR_NMIPENDSET         (0x1 << 31)

-

-#define AIRCR_VECTKEY           0x05FA0000

-#define AIRCR_PRIGROUP_MASK     (0x7 << 8)

-#define AIRCR_PRIGROUP(n)       ((n) << 8)

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-  void NVICEnableVector(uint32_t n, uint32_t prio);

-  void NVICDisableVector(uint32_t n);

-  void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* _NVIC_H_ */

-

-/** @} */

diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h
index c15e10ae2..0ced2caa5 100644
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h
+++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h
@@ -1,8 +1,8 @@
 /**************************************************************************//**

  * @file     core_cm3.h

  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File

- * @version  V2.10

- * @date     19. July 2011

+ * @version  V2.11

+ * @date     08. September 2011

  *

  * @note

  * Copyright (C) 2009-2011 ARM Limited. All rights reserved.

@@ -97,8 +97,8 @@
 

 #endif

 

-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */

-#define __FPU_USED       0

+

+#define __FPU_USED       0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */

 

 #if defined ( __CC_ARM )

   #if defined __TARGET_FPU_VFP

@@ -376,8 +376,16 @@ typedef struct
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

 

 /* SCB Vector Table Offset Register Definitions */

+#if (__CM3_REV < 0x0201)                   /* core r2p1 */

+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */

+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */

+

+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

+#else

 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

+#endif

 

 /* SCB Application Interrupt and Reset Control Register Definitions */

 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

diff --git a/os/ports/GCC/ARMCMx/nvic.c b/os/ports/common/ARMCMx/nvic.c
index 51e4280f2..5c8d52f55 100644
--- a/os/ports/GCC/ARMCMx/nvic.c
+++ b/os/ports/common/ARMCMx/nvic.c
@@ -19,10 +19,10 @@
 */

 

 /**

- * @file    GCC/ARMCMx/nvic.c

+ * @file    common/ARMCMx/nvic.c

  * @brief   Cortex-Mx NVIC support code.

  *

- * @addtogroup ARMCMx_NVIC

+ * @addtogroup COMMON_ARMCMx_NVIC

  * @{

  */

 

@@ -30,14 +30,13 @@
 #include "nvic.h"

 

 /**

- * @brief Sets the priority of an interrupt handler and enables it.

+ * @brief   Sets the priority of an interrupt handler and enables it.

+ * @note    The parameters are not tested for correctness.

  *

- * @param n the interrupt number

- * @param prio the interrupt priority mask

- *

- * @note The parameters are not tested for correctness.

+ * @param[in] n         the interrupt number

+ * @param[in] prio      the interrupt priority mask

  */

-void NVICEnableVector(uint32_t n, uint32_t prio) {

+void nvicEnableVector(uint32_t n, uint32_t prio) {

   unsigned sh = (n & 3) << 3;

 

   NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);

@@ -46,13 +45,12 @@ void NVICEnableVector(uint32_t n, uint32_t prio) {
 }

 

 /**

- * @brief Disables an interrupt handler.

- *

- * @param n the interrupt number

+ * @brief   Disables an interrupt handler.

+ * @note    The parameters are not tested for correctness.

  *

- * @note The parameters are not tested for correctness.

+ * @param[in] n         the interrupt number

  */

-void NVICDisableVector(uint32_t n) {

+void nvicDisableVector(uint32_t n) {

   unsigned sh = (n & 3) << 3;

 

   NVIC_ICER(n >> 5) = 1 << (n & 0x1F);

@@ -60,13 +58,13 @@ void NVICDisableVector(uint32_t n) {
 }

 

 /**

- * @brief Changes the priority of a system handler.

+ * @brief   Changes the priority of a system handler.

+ * @note    The parameters are not tested for correctness.

  *

- * @param handler the system handler number

- * @param prio the system handler priority mask

- * @note The parameters are not tested for correctness.

+ * @param[in] handler   the system handler number

+ * @param[in] prio      the system handler priority mask

  */

-void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {

+void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {

   unsigned sh = (handler & 3) * 8;

 

   SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &

diff --git a/os/ports/GCC/ARMCMx/nvic.h b/os/ports/common/ARMCMx/nvic.h
index b7cc249b5..cce2029d7 100644
--- a/os/ports/GCC/ARMCMx/nvic.h
+++ b/os/ports/common/ARMCMx/nvic.h
@@ -19,18 +19,19 @@
 */

 

 /**

- * @file    GCC/ARMCMx/nvic.h

+ * @file    common/ARMCMx/nvic.h

  * @brief   Cortex-Mx NVIC support macros and structures.

  *

- * @addtogroup ARMCMx_NVIC

+ * @addtogroup COMMON_ARMCMx_NVIC

  * @{

  */

 

 #ifndef _NVIC_H_

 #define _NVIC_H_

 

-/*

- * System vector constants for @p NVICSetSystemHandlerPriority().

+/**

+ * @name System vector numbers

+ * @{

  */

 #define HANDLER_MEM_MANAGE      0       /**< MEM MANAGE vector id.          */

 #define HANDLER_BUS_FAULT       1       /**< BUS FAULT vector id.           */

@@ -44,6 +45,7 @@
 #define HANDLER_RESERVED_9      9

 #define HANDLER_PENDSV          10      /**< PENDSV vector id.              */

 #define HANDLER_SYSTICK         11      /**< SYS TCK vector id.             */

+/** @} */

 

 typedef volatile uint8_t IOREG8;        /**< 8 bits I/O register type.      */

 typedef volatile uint32_t IOREG32;      /**< 32 bits I/O register type.     */

@@ -51,7 +53,7 @@ typedef volatile uint32_t IOREG32;      /**< 32 bits I/O register type.     */
 /**

  * @brief NVIC ITCR register.

  */

-#define NVIC_ITCR               (*((IOREG32 *)0xE000E004))

+#define NVIC_ITCR               (*((IOREG32 *)0xE000E004U))

 

 /**

  * @brief Structure representing the SYSTICK I/O space.

@@ -66,30 +68,30 @@ typedef struct {
 /**

  * @brief SYSTICK peripheral base address.

  */

-#define STBase                  ((CMx_ST *)0xE000E010)

+#define STBase                  ((CMx_ST *)0xE000E010U)

 #define ST_CSR                  (STBase->CSR)

 #define ST_RVR                  (STBase->RVR)

 #define ST_CVR                  (STBase->CVR)

 #define ST_CBVR                 (STBase->CBVR)

 

-#define CSR_ENABLE_MASK         (0x1 << 0)

-#define ENABLE_OFF_BITS         (0 << 0)

-#define ENABLE_ON_BITS          (1 << 0)

-#define CSR_TICKINT_MASK        (0x1 << 1)

-#define   TICKINT_DISABLED_BITS (0 << 1)

-#define   TICKINT_ENABLED_BITS  (1 << 1)

-#define CSR_CLKSOURCE_MASK      (0x1 << 2)

-#define   CLKSOURCE_EXT_BITS    (0 << 2)

-#define   CLKSOURCE_CORE_BITS   (1 << 2)

-#define CSR_COUNTFLAG_MASK      (0x1 << 16)

+#define CSR_ENABLE_MASK         (0x1U << 0)

+#define ENABLE_OFF_BITS         (0U << 0)

+#define ENABLE_ON_BITS          (1U << 0)

+#define CSR_TICKINT_MASK        (0x1U << 1)

+#define   TICKINT_DISABLED_BITS (0U << 1)

+#define   TICKINT_ENABLED_BITS  (1U << 1)

+#define CSR_CLKSOURCE_MASK      (0x1U << 2)

+#define   CLKSOURCE_EXT_BITS    (0U << 2)

+#define   CLKSOURCE_CORE_BITS   (1U << 2)

+#define CSR_COUNTFLAG_MASK      (0x1U << 16)

 

-#define RVR_RELOAD_MASK         (0xFFFFFF << 0)

+#define RVR_RELOAD_MASK         (0xFFFFFFU << 0)

 

-#define CVR_CURRENT_MASK        (0xFFFFFF << 0)

+#define CVR_CURRENT_MASK        (0xFFFFFFU << 0)

 

-#define CBVR_TENMS_MASK         (0xFFFFFF << 0)

-#define CBVR_SKEW_MASK          (0x1 << 30)

-#define CBVR_NOREF_MASK         (0x1 << 31)

+#define CBVR_TENMS_MASK         (0xFFFFFFU << 0)

+#define CBVR_SKEW_MASK          (0x1U << 30)

+#define CBVR_NOREF_MASK         (0x1U << 31)

 

 /**

  * @brief Structure representing the NVIC I/O space.

@@ -113,7 +115,7 @@ typedef struct {
 /**

  * @brief NVIC peripheral base address.

  */

-#define NVICBase                ((CMx_NVIC *)0xE000E100)

+#define NVICBase                ((CMx_NVIC *)0xE000E100U)

 #define NVIC_ISER(n)            (NVICBase->ISER[n])

 #define NVIC_ICER(n)            (NVICBase->ICER[n])

 #define NVIC_ISPR(n)            (NVICBase->ISPR[n])

@@ -152,7 +154,7 @@ typedef struct {
 /**

  * @brief SCB peripheral base address.

  */

-#define SCBBase                 ((CMx_SCB *)0xE000ED00)

+#define SCBBase                 ((CMx_SCB *)0xE000ED00U)

 #define SCB_CPUID               (SCBBase->CPUID)

 #define SCB_ICSR                (SCBBase->ICSR)

 #define SCB_VTOR                (SCBBase->VTOR)

@@ -174,20 +176,20 @@ typedef struct {
 #define SCB_SAR(n)              (SCBBase->SAR[n])

 #define SCB_CPACR               (SCBBase->CPACR)

 

-#define ICSR_VECTACTIVE_MASK    (0x1FF << 0)

-#define ICSR_RETTOBASE          (0x1 << 11)

-#define ICSR_VECTPENDING_MASK   (0x1FF << 12)

-#define ICSR_ISRPENDING         (0x1 << 22)

-#define ICSR_ISRPREEMPT         (0x1 << 23)

-#define ICSR_PENDSTCLR          (0x1 << 25)

-#define ICSR_PENDSTSET          (0x1 << 26)

-#define ICSR_PENDSVCLR          (0x1 << 27)

-#define ICSR_PENDSVSET          (0x1 << 28)

+#define ICSR_VECTACTIVE_MASK    (0x1FFU << 0)

+#define ICSR_RETTOBASE          (0x1U << 11)

+#define ICSR_VECTPENDING_MASK   (0x1FFU << 12)

+#define ICSR_ISRPENDING         (0x1U << 22)

+#define ICSR_ISRPREEMPT         (0x1U << 23)

+#define ICSR_PENDSTCLR          (0x1U << 25)

+#define ICSR_PENDSTSET          (0x1U << 26)

+#define ICSR_PENDSVCLR          (0x1U << 27)

+#define ICSR_PENDSVSET          (0x1U << 28)

 #define ICSR_NMIPENDSET         (0x1U << 31)

 

-#define AIRCR_VECTKEY           0x05FA0000

-#define AIRCR_PRIGROUP_MASK     (0x7 << 8)

-#define AIRCR_PRIGROUP(n)       ((n) << 8)

+#define AIRCR_VECTKEY           0x05FA0000U

+#define AIRCR_PRIGROUP_MASK     (0x7U << 8)

+#define AIRCR_PRIGROUP(n)       ((n##U) << 8)

 

 typedef struct {

   IOREG32       unused1[1];

@@ -201,7 +203,7 @@ typedef struct {
 /**

  * @brief FPU peripheral base address.

  */

-#define FPUBase                 ((CMx_FPU *)0xE000EF30L)

+#define FPUBase                 ((CMx_FPU *)0xE000EF30U)

 #define SCB_FPCCR               (FPUBase->FPCCR)

 #define SCB_FPCAR               (FPUBase->FPCAR)

 #define SCB_FPDSCR              (FPUBase->FPDSCR)

@@ -221,14 +223,14 @@ typedef struct {
 #define FPDSCR_AHP              (0x1U << 26)

 #define FPDSCR_DN               (0x1U << 25)

 #define FPDSCR_FZ               (0x1U << 24)

-#define FPDSCR_RMODE(n)         ((n) << 22)

+#define FPDSCR_RMODE(n)         ((n##U) << 22)

 

 #ifdef __cplusplus

 extern "C" {

 #endif

-  void NVICEnableVector(uint32_t n, uint32_t prio);

-  void NVICDisableVector(uint32_t n);

-  void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);

+  void nvicEnableVector(uint32_t n, uint32_t prio);

+  void nvicDisableVector(uint32_t n);

+  void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);

 #ifdef __cplusplus

 }

 #endif