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author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-23 15:48:55 +0000 |
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committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-23 15:48:55 +0000 |
commit | c39d08fc2ae9c43f73114e24292520306bddde19 (patch) | |
tree | 7bae8c26f8e20566aba8755f0cd3bb34d2ac4f87 /os/ports/IAR/ARMCMx | |
parent | d2721c36a6d74fd18de7e4de95fdd166083e343e (diff) | |
download | ChibiOS-c39d08fc2ae9c43f73114e24292520306bddde19.tar.gz ChibiOS-c39d08fc2ae9c43f73114e24292520306bddde19.tar.bz2 ChibiOS-c39d08fc2ae9c43f73114e24292520306bddde19.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3384 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports/IAR/ARMCMx')
-rw-r--r-- | os/ports/IAR/ARMCMx/port.dox | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/os/ports/IAR/ARMCMx/port.dox b/os/ports/IAR/ARMCMx/port.dox index 3e10318ce..b85b6fa07 100644 --- a/os/ports/IAR/ARMCMx/port.dox +++ b/os/ports/IAR/ARMCMx/port.dox @@ -70,8 +70,7 @@ * not globally masked but only interrupts with higher priority can preempt
* the current handler. The processor is running in exception-privileged
* mode.
- * - <b>Serving Fast Interrupt</b>. This state is not implemented in the
- * ARMv6-M implementation.
+ * - <b>Serving Fast Interrupt</b>. Not implemented in compact kernel mode.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
@@ -109,9 +108,13 @@ * not globally masked but only interrupts with higher priority can preempt
* the current handler. The processor is running in exception-privileged
* mode.
- * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
- * but it is not possible to switch to the I-Locked state because fast
- * interrupts can preempt the kernel critical zone.
+ * - <b>Serving Fast Interrupt</b>. Fast interrupts are defined as interrupt
+ * sources having higher priority level than the kernel
+ * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
+ * the I-Locked state because fast interrupts can preempt the kernel
+ * critical zone.<br>
+ * This state is not implemented in the ARMv6-M implementation because
+ * priority masking is not present in this architecture.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
@@ -126,19 +129,6 @@ * stack where all the interrupts and exceptions are processed.
* - The threads are started in thread-privileged mode.
* - Interrupt nesting and the other advanced core/NVIC features are supported.
- * - When using an STM32 one of the following macros must be defined on the
- * compiler command line or in a file named <tt>board.h</tt>:
- * - @p STM32F10X_LD
- * - @p STM32F10X_LD_VL
- * - @p STM32F10X_MD
- * - @p STM32F10X_MD_VL
- * - @p STM32F10X_HD
- * - @p STM32F10X_XL
- * - @p STM32F10X_CL
- * .
- * This is required in order to include a vectors table with the correct
- * length for the STM32 model, see the file
- * <tt>./os/ports/IAR/ARMCMx/STM32/vectors.s</tt>.
* - The Cortex-Mx port is perfectly generic, support for more devices can be
* easily added by adding a subdirectory under <tt>./os/ports/IAR/ARMCMx</tt>
* and giving it the name of the new device, then copy the files from another
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