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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-06-01 17:56:23 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-06-01 17:56:23 +0000 |
| commit | 33ecba3fd8ea17494b7154d20e677dd50f57b510 (patch) | |
| tree | 60bbb4dccbe930a0c8e2850d7e7df982c1aa3c54 /os/ports/GCC/ARMCMx/chcore_v6m.h | |
| parent | 03c0617a9fe69f113d3a55b3760a566643475394 (diff) | |
| download | ChibiOS-33ecba3fd8ea17494b7154d20e677dd50f57b510.tar.gz ChibiOS-33ecba3fd8ea17494b7154d20e677dd50f57b510.tar.bz2 ChibiOS-33ecba3fd8ea17494b7154d20e677dd50f57b510.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3005 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports/GCC/ARMCMx/chcore_v6m.h')
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v6m.h | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index 3154bde56..e6aeabc2d 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -34,20 +34,12 @@ /*===========================================================================*/
/**
- * @brief BASEPRI level within kernel lock.
- * @note The ARMv6-M architecture does not implement the BASEPRI register
- * so the kernel always masks the whole priority range during
- * a kernel lock.
- */
-#define CORTEX_BASEPRI_KERNEL 0
-
-/**
* @brief PendSV priority level.
- * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
+ * @note This priority is enforced to be equal to @p 0,
* this handler always have the highest priority that cannot preempt
* the kernel.
*/
-#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
+#define CORTEX_PRIORITY_PENDSV 0
/*===========================================================================*/
/* Port configurable parameters. */
@@ -64,7 +56,7 @@ /**
* @brief Macro defining the specific ARM architecture.
*/
-#define CH_ARCHITECTURE_ARM_v7M
+#define CH_ARCHITECTURE_ARM_v6M
/**
* @brief Name of the implemented architecture.
@@ -84,6 +76,13 @@ /* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -244,6 +243,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V6M_H_ */
/** @} */
|