git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3005 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 55 insertions, 36 deletions

diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h
index 42df48a09..5d47a6699 100644
--- a/os/ports/GCC/ARMCMx/chcore.h
+++ b/os/ports/GCC/ARMCMx/chcore.h
@@ -29,12 +29,18 @@
 #ifndef _CHCORE_H_

 #define _CHCORE_H_

 

-#include "nvic.h"

-

 /*===========================================================================*/

-/* Port constants.                                                           */

+/* Port constants (common).                                                  */

 /*===========================================================================*/

 

+/* Added to make the header stand-alone when included from asm.*/

+#ifndef FALSE

+#define FALSE       0

+#endif

+#ifndef TRUE

+#define TRUE        (!FALSE)

+#endif

+

 #define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */

 #define CORTEX_M1                       1   /**< @brief Cortex-M1 variant.  */

 #define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */

@@ -69,14 +75,8 @@
  */

 #define CORTEX_MAXIMUM_PRIORITY         0

 

-/**

- * @brief   Disabled value for BASEPRI register.

- * @note    ARMv7-M architecture only.

- */

-#define CORTEX_BASEPRI_DISABLED         0

-

 /*===========================================================================*/

-/* Port macros.                                                              */

+/* Port macros (common).                                                     */

 /*===========================================================================*/

 

 /**

@@ -92,7 +92,7 @@
   ((n) << (8 - CORTEX_PRIORITY_BITS))

 

 /*===========================================================================*/

-/* Port configurable parameters.                                             */

+/* Port configurable parameters (common).                                    */

 /*===========================================================================*/

 

 /**

@@ -156,11 +156,11 @@
 #endif

 

 /*===========================================================================*/

-/* Port derived parameters.                                                  */

+/* Port derived parameters (common).                                         */

 /*===========================================================================*/

 

 /*===========================================================================*/

-/* Port exported info.                                                       */

+/* Port exported info (common).                                              */

 /*===========================================================================*/

 

 /**

@@ -177,6 +177,17 @@
 /* Port implementation part (common).                                        */

 /*===========================================================================*/

 

+/* Includes the sub-architecture-specific part.*/

+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)

+#include "chcore_v6m.h"

+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)

+#include "chcore_v7m.h"

+#endif

+

+#if !defined(_FROM_ASM_)

+

+#include "nvic.h"

+

 /**

  * @brief   Stack and memory alignment enforcement.

  */

@@ -193,11 +204,6 @@ typedef uint32_t stkalign_t __attribute__ ((aligned (4)));
 #error "invalid stack alignment selected"

 #endif

 

-/**

- * @brief   Generic ARM register.

- */

-typedef void *regarm_t;

-

 #if defined(__DOXYGEN__)

 /**

  * @brief   Interrupt saved context.

@@ -262,12 +268,7 @@ struct context {
  */

 #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]

 

-/* Includes the architecture-specific implementation part.*/

-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)

-#include "chcore_v6m.h"

-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)

-#include "chcore_v7m.h"

-#endif

+#endif /* _FROM_ASM_ */

 

 #endif /* _CHCORE_H_ */

 

diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h
index 3154bde56..e6aeabc2d 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.h
@@ -34,20 +34,12 @@
 /*===========================================================================*/

 

 /**

- * @brief   BASEPRI level within kernel lock.

- * @note    The ARMv6-M architecture does not implement the BASEPRI register

- *          so the kernel always masks the whole priority range during

- *          a kernel lock.

- */

-#define CORTEX_BASEPRI_KERNEL           0

-

-/**

  * @brief   PendSV priority level.

- * @note    This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,

+ * @note    This priority is enforced to be equal to @p 0,

  *          this handler always have the highest priority that cannot preempt

  *          the kernel.

  */

-#define CORTEX_PRIORITY_PENDSV          CORTEX_BASEPRI_KERNEL

+#define CORTEX_PRIORITY_PENDSV          0

 

 /*===========================================================================*/

 /* Port configurable parameters.                                             */

@@ -64,7 +56,7 @@
 /**

  * @brief   Macro defining the specific ARM architecture.

  */

-#define CH_ARCHITECTURE_ARM_v7M

+#define CH_ARCHITECTURE_ARM_v6M

 

 /**

  * @brief   Name of the implemented architecture.

@@ -84,6 +76,13 @@
 /* Port implementation part.                                                 */

 /*===========================================================================*/

 

+#if !defined(_FROM_ASM_)

+

+/**

+ * @brief   Generic ARM register.

+ */

+typedef void *regarm_t;

+

 #if !defined(__DOXYGEN__)

 struct extctx {

   regarm_t      r0;

@@ -244,6 +243,8 @@ extern "C" {
 }

 #endif

 

+#endif /* _FROM_ASM_ */

+

 #endif /* _CHCORE_V6M_H_ */

 

 /** @} */

diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h
index 7a7eaeb53..297bd4e54 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v7m.h
@@ -33,6 +33,11 @@
 /* Port constants.                                                           */

 /*===========================================================================*/

 

+/**

+ * @brief   Disabled value for BASEPRI register.

+ */

+#define CORTEX_BASEPRI_DISABLED         0

+

 /*===========================================================================*/

 /* Port configurable parameters.                                             */

 /*===========================================================================*/

@@ -88,6 +93,7 @@
 /* Port exported info.                                                       */

 /*===========================================================================*/

 

+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

 /**

  * @brief   Macro defining the specific ARM architecture.

  */

@@ -101,9 +107,11 @@
 /**

  * @brief   Name of the architecture variant.

  */

-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

 #define CH_CORE_VARIANT_NAME            "Cortex-M3"

+

 #elif (CORTEX_MODEL == CORTEX_M4)

+#define CH_ARCHITECTURE_ARM_v7ME

+#define CH_ARCHITECTURE_NAME            "ARMv7-ME"

 #define CH_CORE_VARIANT_NAME            "Cortex-M4"

 #endif

 

@@ -120,6 +128,13 @@
 /* Port implementation part.                                                 */

 /*===========================================================================*/

 

+#if !defined(_FROM_ASM_)

+

+/**

+ * @brief   Generic ARM register.

+ */

+typedef void *regarm_t;

+

 #if !defined(__DOXYGEN__)

 struct extctx {

   regarm_t      r0;

@@ -315,6 +330,8 @@ extern "C" {
 }

 #endif

 

+#endif /* _FROM_ASM_ */

+

 #endif /* _CHCORE_V7M_H_ */

 

 /** @} */