git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1195 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 227 insertions, 11 deletions

diff --git a/os/io/platforms/AT91SAM7X/mac_lld.c b/os/io/platforms/AT91SAM7X/mac_lld.c
index d7a7a947f..ac08abb35 100644
--- a/os/io/platforms/AT91SAM7X/mac_lld.c
+++ b/os/io/platforms/AT91SAM7X/mac_lld.c
@@ -28,9 +28,8 @@
 

 #include <ch.h>

 #include <mac.h>

-#include <phy.h>

+#include <mii.h>

 

-#include "mii.h"

 #include "at91lib/aic.h"

 

 /**

@@ -125,7 +124,7 @@ CH_IRQ_HANDLER(irq_handler) {
 void mac_lld_init(void) {

   unsigned i;

 

-  phyInit();

+  miiInit();

   macObjectInit(&ETH1);

 

   /*

@@ -147,7 +146,7 @@ void mac_lld_init(void) {
   /*

    * Associated PHY initialization.
    */

-  phyReset(&ETH1);

+  miiReset(&ETH1);

 

   /*

    * EMAC pins setup and clock enable. Note, PB18 is not included because it is

@@ -180,8 +179,8 @@ void mac_lld_init(void) {
    * PHY device identification.

    */

   AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;

-  if ((phyGet(&ETH1, MII_PHYSID1) != (MII_KS8721_ID >> 16)) ||

-      ((phyGet(&ETH1, MII_PHYSID2) & 0xFFF0) != (MII_KS8721_ID & 0xFFF0)))

+  if ((miiGet(&ETH1, MII_PHYSID1) != (MII_KS8721_ID >> 16)) ||

+      ((miiGet(&ETH1, MII_PHYSID2) & 0xFFF0) != (MII_KS8721_ID & 0xFFF0)))

     chSysHalt();

   AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;

 #endif

@@ -443,17 +442,17 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) {
   uint32_t ncfgr, bmsr, bmcr, lpa;

 

   AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;

-  (void)phyGet(macp, MII_BMSR);

-  bmsr = phyGet(macp, MII_BMSR);

+  (void)miiGet(macp, MII_BMSR);

+  bmsr = miiGet(macp, MII_BMSR);

   if (!(bmsr & BMSR_LSTATUS)) {

     AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;

     return link_up = FALSE;

   }

 

   ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);

-  bmcr = phyGet(macp, MII_BMCR);

+  bmcr = miiGet(macp, MII_BMCR);

   if (bmcr & BMCR_ANENABLE) {

-    lpa = phyGet(macp, MII_LPA);

+    lpa = miiGet(macp, MII_LPA);

     if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))

       ncfgr |= AT91C_EMAC_SPD;

     if (lpa & (LPA_10FULL | LPA_100FULL))

diff --git a/os/io/platforms/AT91SAM7X/mii_lld.c b/os/io/platforms/AT91SAM7X/mii_lld.c
new file mode 100644
index 000000000..56fd87a51
--- /dev/null
+++ b/os/io/platforms/AT91SAM7X/mii_lld.c
@@ -0,0 +1,115 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file AT91SAM7X/mii_lld.c

+ * @brief AT91SAM7X low level MII driver code

+ * @addtogroup AT91SAM7X_MII

+ * @{

+ */

+

+#include <ch.h>

+#include <mac.h>

+#include <mii.h>

+

+/**

+ * @brief Low level MII driver initialization.

+ */

+void mii_lld_init(void) {

+

+}

+

+/**

+ * @brief Resets a PHY device.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ */

+void mii_lld_reset(MACDriver *macp) {

+

+  /*

+   * Disables the pullups on all the pins that are latched on reset by the PHY.

+   * The status latched into the PHY is:

+   *   PHYADDR  = 00001

+   *   PCS_LPBK = 0 (disabled)

+   *   ISOLATE  = 0 (disabled)

+   *   RMIISEL  = 0 (MII mode)

+   *   RMIIBTB  = 0 (BTB mode disabled)

+   *   SPEED    = 1 (100mbps)

+   *   DUPLEX   = 1 (full duplex)

+   *   ANEG_EN  = 1 (auto negotiation enabled)

+   */

+  AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS;

+

+#ifdef PIOB_PHY_PD_MASK

+  /*

+   * PHY power control.

+   */

+  AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK;       // Becomes an output.

+  AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;     // Default pullup disabled.

+  AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK;      // Output to high level.

+#endif

+

+  /*

+   * PHY reset by pulsing the NRST pin.

+   */

+  AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100;

+  AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;

+  while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))

+    ;

+}

+

+/**

+ * @brief Reads a PHY register through the MII interface.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @return The register value.

+ */

+phyreg_t mii_lld_get(MACDriver *macp, phyaddr_t addr) {

+

+  AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) |            /* SOF */

+                              (0b10 << 28) |            /* RW */

+                              (PHY_ADDRESS << 23) |     /* PHYA */

+                              (addr << 18) |            /* REGA */

+                              (0b10 << 16);             /* CODE */

+  while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))

+    ;

+  return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF);

+}

+

+/**

+ * @brief Writes a PHY register through the MII interface.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @param value the new register value

+ */

+void mii_lld_put(MACDriver *macp, phyaddr_t addr, phyreg_t value) {

+

+  AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) |            /* SOF */

+                              (0b01 << 28) |            /* RW */

+                              (PHY_ADDRESS << 23) |     /* PHYA */

+                              (addr << 18) |            /* REGA */

+                              (0b10 << 16) |            /* CODE */

+                              value;

+  while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))

+    ;

+}

+

+/** @} */

diff --git a/os/io/platforms/AT91SAM7X/mii_lld.h b/os/io/platforms/AT91SAM7X/mii_lld.h
new file mode 100644
index 000000000..f54ee0508
--- /dev/null
+++ b/os/io/platforms/AT91SAM7X/mii_lld.h
@@ -0,0 +1,91 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file AT91SAM7X/mii_lld.h

+ * @brief AT91SAM7X low level MII driver header

+ * @addtogroup AT91SAM7X_MII

+ * @{

+ */

+

+#ifndef _MII_LLD_H_

+#define _MII_LLD_H_

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief PHY manufacturer and model.

+ */

+#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__)

+#define PHY_HARDWARE            PHY_MICREL_KS8721

+#endif

+

+/*===========================================================================*/

+/* PHY specific constants.                                                   */

+/*===========================================================================*/

+

+#define PHY_MICREL_KS8721       0

+

+#if PHY_HARDWARE == PHY_MICREL_KS8721

+#define PHY_ADDRESS             1

+#endif

+

+/**

+ * @brief Pins latched by the PHY at reset.
+ */

+#define PHY_LATCHED_PINS        (AT91C_PB4_ECRS          | AT91C_PB5_ERX0  | \

+                                 AT91C_PB6_ERX1          | AT91C_PB7_ERXER | \

+                                 AT91C_PB13_ERX2         | AT91C_PB14_ERX3 | \

+                                 AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \

+                                 AT91C_PIO_PB26)

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief Type of a PHY register value.

+ */

+typedef uint16_t phyreg_t;

+

+/**

+ * @brief Type of a PHY register address.

+ */

+typedef uint8_t phyaddr_t;

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void mii_lld_init(void);

+  void mii_lld_reset(MACDriver *macp);

+  phyreg_t mii_lld_get(MACDriver *macp, phyaddr_t addr);

+  void mii_lld_put(MACDriver *macp, phyaddr_t addr, phyreg_t value);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _MII_LLD_H_ */

+

+/** @} */

diff --git a/os/io/platforms/AT91SAM7X/platform.dox b/os/io/platforms/AT91SAM7X/platform.dox
index 6176140ad..1e5b7f8c8 100644
--- a/os/io/platforms/AT91SAM7X/platform.dox
+++ b/os/io/platforms/AT91SAM7X/platform.dox
@@ -66,8 +66,19 @@
  */

 

 /**

- * @defgroup AT91SAM7X_EMAC AT91SAM7X EMAC Support

+ * @defgroup AT91SAM7X_MAC AT91SAM7X EMAC Support

  * @brief EMAC peripheral support.

+ * @details the @ref MAC supports the AT91SAM7X EMAC peripheral.

+ *

+ * @ingroup AT91SAM7X

+ */

+

+/**

+ * @defgroup AT91SAM7X_MII AT91SAM7X MII Support

+ * @brief EMAC peripheral support.

+ * @details the @ref MII supports the AT91SAM7X EMAC peripheral communicating

+ *          with an external PHY transceiver. The driver currently supports

+ *          only the Micrel KS8721 PHY module.

  *

  * @ingroup AT91SAM7X

  */