git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1195 35acf78f-673a-0410-8e92-d51de3d6d3f4

10 files changed, 660 insertions, 15 deletions

diff --git a/os/io/io.dox b/os/io/io.dox
index f0ab3c2db..3e425f023 100644
--- a/os/io/io.dox
+++ b/os/io/io.dox
@@ -17,7 +17,6 @@
     along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

 

-

 /**

  * @defgroup IO I/O

  * @brief I/O related services.

@@ -47,6 +46,7 @@
  * The I/O subsystem currently includes support for:

  * - @ref PAL.

  * - @ref SERIAL.

+ * - @ref MAC

  * .

  */

 

@@ -123,7 +123,7 @@
  * to notify the application about incoming data, outgoing data and other I/O

  * events.<br>

  * The  module also contains functions that make the implementation of the

- * interrupt service routines much easier.<br>

+ * interrupt service routines much easier.

  *

  * @ingroup IO

  */

@@ -135,3 +135,42 @@
  *

  * @ingroup SERIAL

  */

+

+/**

+ * @defgroup MAC MAC Driver

+ * @brief Generic MAC driver.

+ * @details This module implements a generic interface for MAC (Media

+ *          Access Control) drivers, as example Ethernet controllers.

+ *

+ * @ingroup IO

+ */

+

+/**

+ * @defgroup MAC_LLD MAC Low Level Driver

+ * @brief @ref MAC low level driver template.

+ * @details This file is a template for a MAC low level driver.

+ *

+ * @ingroup MAC

+ */

+

+/**

+ * @defgroup MII MII Driver

+ * @brief Generic MII driver.

+ * @details This module implements a generic interface for MII (Media

+ *          Independent Interface) drivers.

+ *          The MII/RMII/GMII/RGMII/SGMII buses are standard interfaces meant

+ *          to connect a @ref MAC block to a PHY transceiver.<br>

+ *          A @ref MII is usually used from within a @ref MAC and is not

+ *          meant to be used directly from the application code.

+ *

+ * @ingroup IO

+ */

+

+/**

+ * @defgroup MII_LLD MII Low Level Driver

+ * @brief @ref MII low level driver template.

+ * @details This file is a template for a MII low level driver.

+ *

+ * @ingroup MII

+ */

+ 
\ No newline at end of file
diff --git a/os/io/mac.c b/os/io/mac.c
index 6754bf78f..809ea5fd1 100644
--- a/os/io/mac.c
+++ b/os/io/mac.c
@@ -109,7 +109,6 @@ msg_t macWaitTransmitDescriptor(MACDriver *macp,
  * @brief Releases a transmit descriptor and starts the transmission of the

  *        enqueued data as a single frame.

  *
- * @param[in] macp pointer to the @p MACDriver object

  * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
  */

 void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) {

@@ -157,7 +156,6 @@ msg_t macWaitReceiveDescriptor(MACDriver *macp,
  * @details The descriptor and its buffer are made available for more incoming

  *          frames.

  *

- * @param[in] macp pointer to the @p MACDriver object

  * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure

  */

 void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) {

diff --git a/os/io/mii.c b/os/io/mii.c
new file mode 100644
index 000000000..da36db9d2
--- /dev/null
+++ b/os/io/mii.c
@@ -0,0 +1,37 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file mii.c

+ * @brief mii Driver code.

+ * @addtogroup MII

+ * @{

+ */

+

+#include <ch.h>

+#include <mac.h>

+#include <mii.h>

+

+/*

+ * Currently there is no code, everything is done in the header, you may 

+ * omit this file from the project but this may change in future releases.

+ * The file is here because the driver's naming pattern.

+ */

+ 

+/** @} */

diff --git a/os/io/mii.h b/os/io/mii.h
new file mode 100644
index 000000000..a236c6dc3
--- /dev/null
+++ b/os/io/mii.h
@@ -0,0 +1,220 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/*

+ * Parts of this file are borrowed by the Linux include file linux/mii.h:

+ * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)

+ */

+

+/**

+ * @file mii.h

+ * @brief MII Driver macros and structures.

+ * @addtogroup MII

+ * @{

+ */

+

+#ifndef _MII_H_

+#define _MII_H_

+

+#include "mac_lld.h"

+#include "mii_lld.h"

+

+/*

+ * Generic MII registers. Note, not all registers are present on all PHY

+ * devices and some extra registers may be present.

+ */

+#define MII_BMCR                0x00    /**< Basic mode control register.   */

+#define MII_BMSR                0x01    /**< Basic mode status register.    */

+#define MII_PHYSID1             0x02    /**< PHYS ID 1.                     */

+#define MII_PHYSID2             0x03    /**< PHYS ID 2.                     */

+#define MII_ADVERTISE           0x04    /**< Advertisement control reg.     */

+#define MII_LPA                 0x05    /**< Link partner ability reg.      */

+#define MII_EXPANSION           0x06    /**< Expansion register.            */

+#define MII_CTRL1000            0x09    /**< 1000BASE-T control.            */

+#define MII_STAT1000            0x0a    /**< 1000BASE-T status.             */

+#define MII_ESTATUS             0x0f    /**< Extended Status.               */

+#define MII_DCOUNTER            0x12    /**< Disconnect counter.            */

+#define MII_FCSCOUNTER          0x13    /**< False carrier counter.         */

+#define MII_NWAYTEST            0x14    /**< N-way auto-neg test reg.       */

+#define MII_RERRCOUNTER         0x15    /**< Receive error counter.         */

+#define MII_SREVISION           0x16    /**< Silicon revision.              */

+#define MII_RESV1               0x17    /**< Reserved.                      */

+#define MII_LBRERROR            0x18    /**< Lpback, rx, bypass error.      */

+#define MII_PHYADDR             0x19    /**< PHY address.                   */

+#define MII_RESV2               0x1a    /**< Reserved.                      */

+#define MII_TPISTATUS           0x1b    /**< TPI status for 10mbps.         */

+#define MII_NCONFIG             0x1c    /**< Network interface config.      */

+

+/*

+ * Basic mode control register.

+ */

+#define BMCR_RESV               0x003f  /**< Unused.                        */

+#define BMCR_SPEED1000          0x0040  /**< MSB of Speed (1000).           */

+#define BMCR_CTST               0x0080  /**< Collision test.                */

+#define BMCR_FULLDPLX           0x0100  /**< Full duplex.                   */

+#define BMCR_ANRESTART          0x0200  /**< Auto negotiation restart.      */

+#define BMCR_ISOLATE            0x0400  /**< Disconnect DP83840 from MII.   */

+#define BMCR_PDOWN              0x0800  /**< Powerdown.                     */

+#define BMCR_ANENABLE           0x1000  /**< Enable auto negotiation.       */

+#define BMCR_SPEED100           0x2000  /**< Select 100Mbps.                */

+#define BMCR_LOOPBACK           0x4000  /**< TXD loopback bits.             */

+#define BMCR_RESET              0x8000  /**< Reset.                         */

+

+/*

+ * Basic mode status register.

+ */

+#define BMSR_ERCAP              0x0001  /**< Ext-reg capability.            */

+#define BMSR_JCD                0x0002  /**< Jabber detected.               */

+#define BMSR_LSTATUS            0x0004  /**< Link status.                   */

+#define BMSR_ANEGCAPABLE        0x0008  /**< Able to do auto-negotiation.   */

+#define BMSR_RFAULT             0x0010  /**< Remote fault detected.         */

+#define BMSR_ANEGCOMPLETE       0x0020  /**< Auto-negotiation complete.     */

+#define BMSR_RESV               0x00c0  /**< Unused.                        */

+#define BMSR_ESTATEN            0x0100  /**< Extended Status in R15.        */

+#define BMSR_100HALF2           0x0200  /**< Can do 100BASE-T2 HDX.         */

+#define BMSR_100FULL2           0x0400  /**< Can do 100BASE-T2 FDX.         */

+#define BMSR_10HALF             0x0800  /**< Can do 10mbps, half-duplex.    */

+#define BMSR_10FULL             0x1000  /**< Can do 10mbps, full-duplex.    */

+#define BMSR_100HALF            0x2000  /**< Can do 100mbps, half-duplex.   */

+#define BMSR_100FULL            0x4000  /**< Can do 100mbps, full-duplex.   */

+#define BMSR_100BASE4           0x8000  /**< Can do 100mbps, 4k packets.    */

+

+/*

+ * Advertisement control register.

+ */

+#define ADVERTISE_SLCT          0x001f  /**< Selector bits.                 */

+#define ADVERTISE_CSMA          0x0001  /**< Only selector supported.       */

+#define ADVERTISE_10HALF        0x0020  /**< Try for 10mbps half-duplex.    */

+#define ADVERTISE_1000XFULL     0x0020  /**< Try for 1000BASE-X full-duplex.*/

+#define ADVERTISE_10FULL        0x0040  /**< Try for 10mbps full-duplex.    */

+#define ADVERTISE_1000XHALF     0x0040  /**< Try for 1000BASE-X half-duplex.*/

+#define ADVERTISE_100HALF       0x0080  /**< Try for 100mbps half-duplex.   */

+#define ADVERTISE_1000XPAUSE    0x0080  /**< Try for 1000BASE-X pause.      */

+#define ADVERTISE_100FULL       0x0100  /**< Try for 100mbps full-duplex.   */

+#define ADVERTISE_1000XPSE_ASYM 0x0100  /**< Try for 1000BASE-X asym pause. */

+#define ADVERTISE_100BASE4      0x0200  /**< Try for 100mbps 4k packets.    */

+#define ADVERTISE_PAUSE_CAP     0x0400  /**< Try for pause.                 */

+#define ADVERTISE_PAUSE_ASYM    0x0800  /**< Try for asymetric pause.       */

+#define ADVERTISE_RESV          0x1000  /**< Unused.                        */

+#define ADVERTISE_RFAULT        0x2000  /**< Say we can detect faults.      */

+#define ADVERTISE_LPACK         0x4000  /**< Ack link partners response.    */

+#define ADVERTISE_NPAGE         0x8000  /**< Next page bit.                 */

+

+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \

+                        ADVERTISE_CSMA)

+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \

+                       ADVERTISE_100HALF | ADVERTISE_100FULL)

+

+/*

+ * Link partner ability register.

+ */

+#define LPA_SLCT                0x001f  /**< Same as advertise selector.    */

+#define LPA_10HALF              0x0020  /**< Can do 10mbps half-duplex.     */

+#define LPA_1000XFULL           0x0020  /**< Can do 1000BASE-X full-duplex. */

+#define LPA_10FULL              0x0040  /**< Can do 10mbps full-duplex.     */

+#define LPA_1000XHALF           0x0040  /**< Can do 1000BASE-X half-duplex. */

+#define LPA_100HALF             0x0080  /**< Can do 100mbps half-duplex.    */

+#define LPA_1000XPAUSE          0x0080  /**< Can do 1000BASE-X pause.       */

+#define LPA_100FULL             0x0100  /**< Can do 100mbps full-duplex.    */

+#define LPA_1000XPAUSE_ASYM     0x0100  /**< Can do 1000BASE-X pause asym.  */

+#define LPA_100BASE4            0x0200  /**< Can do 100mbps 4k packets.     */

+#define LPA_PAUSE_CAP           0x0400  /**< Can pause.                     */

+#define LPA_PAUSE_ASYM          0x0800  /**< Can pause asymetrically.       */

+#define LPA_RESV                0x1000  /**< Unused.                        */

+#define LPA_RFAULT              0x2000  /**< Link partner faulted.          */

+#define LPA_LPACK               0x4000  /**< Link partner acked us.         */

+#define LPA_NPAGE               0x8000  /**< Next page bit.                 */

+

+#define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)

+#define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)

+

+/*

+ * Expansion register for auto-negotiation.

+ */

+#define EXPANSION_NWAY          0x0001  /**< Can do N-way auto-nego.        */

+#define EXPANSION_LCWP          0x0002  /**< Got new RX page code word.     */

+#define EXPANSION_ENABLENPAGE   0x0004  /**< This enables npage words.      */

+#define EXPANSION_NPCAPABLE     0x0008  /**< Link partner supports npage.   */

+#define EXPANSION_MFAULTS       0x0010  /**< Multiple faults detected.      */

+#define EXPANSION_RESV          0xffe0  /**< Unused.                        */

+

+#define ESTATUS_1000_TFULL      0x2000  /**< Can do 1000BT Full.            */

+#define ESTATUS_1000_THALF      0x1000  /**< Can do 1000BT Half.            */

+

+/*

+ * N-way test register.

+ */

+#define NWAYTEST_RESV1          0x00ff  /**< Unused.                        */

+#define NWAYTEST_LOOPBACK       0x0100  /**< Enable loopback for N-way.     */

+#define NWAYTEST_RESV2          0xfe00  /**< Unused.                        */

+

+/*

+ * 1000BASE-T Control register.

+ */

+#define ADVERTISE_1000FULL      0x0200  /**< Advertise 1000BASE-T full duplex.*/

+#define ADVERTISE_1000HALF      0x0100  /**< Advertise 1000BASE-T half duplex.*/

+

+/*

+ * 1000BASE-T Status register.

+ */

+#define LPA_1000LOCALRXOK       0x2000  /**< Link partner local receiver status.*/

+#define LPA_1000REMRXOK         0x1000  /**< Link partner remote receiver status.*/

+#define LPA_1000FULL            0x0800  /**< Link partner 1000BASE-T full duplex.*/

+#define LPA_1000HALF            0x0400  /**< Link partner 1000BASE-T half duplex.*/

+

+/*

+ * PHY identifiers.

+ */

+#define MII_DM9161_ID     0x0181b8a0

+#define MII_AM79C875_ID   0x00225540

+#define MII_KS8721_ID     0x00221610

+

+/**

+ * @brief MII Driver initialization.

+ */

+#define miiInit() mii_lld_init()

+

+/**

+ * Resets a MII device.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ */

+#define miiReset(macp) mii_lld_reset(macp)

+

+/**

+ * @brief Reads a MII register.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @return The register value.

+ */

+#define miiGet(macp, addr) mii_lld_get(macp, addr)

+

+/**

+ * @brief Writes a MII register.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @param value the new register value

+ */

+#define miiPut(macp, addr, value) mii_lld_put(macp, addr, value)

+

+#endif /**< _MII_H_ */

+

+/** @} */

diff --git a/os/io/platforms/AT91SAM7X/mac_lld.c b/os/io/platforms/AT91SAM7X/mac_lld.c
index d7a7a947f..ac08abb35 100644
--- a/os/io/platforms/AT91SAM7X/mac_lld.c
+++ b/os/io/platforms/AT91SAM7X/mac_lld.c
@@ -28,9 +28,8 @@
 

 #include <ch.h>

 #include <mac.h>

-#include <phy.h>

+#include <mii.h>

 

-#include "mii.h"

 #include "at91lib/aic.h"

 

 /**

@@ -125,7 +124,7 @@ CH_IRQ_HANDLER(irq_handler) {
 void mac_lld_init(void) {

   unsigned i;

 

-  phyInit();

+  miiInit();

   macObjectInit(&ETH1);

 

   /*

@@ -147,7 +146,7 @@ void mac_lld_init(void) {
   /*

    * Associated PHY initialization.
    */

-  phyReset(&ETH1);

+  miiReset(&ETH1);

 

   /*

    * EMAC pins setup and clock enable. Note, PB18 is not included because it is

@@ -180,8 +179,8 @@ void mac_lld_init(void) {
    * PHY device identification.

    */

   AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;

-  if ((phyGet(&ETH1, MII_PHYSID1) != (MII_KS8721_ID >> 16)) ||

-      ((phyGet(&ETH1, MII_PHYSID2) & 0xFFF0) != (MII_KS8721_ID & 0xFFF0)))

+  if ((miiGet(&ETH1, MII_PHYSID1) != (MII_KS8721_ID >> 16)) ||

+      ((miiGet(&ETH1, MII_PHYSID2) & 0xFFF0) != (MII_KS8721_ID & 0xFFF0)))

     chSysHalt();

   AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;

 #endif

@@ -443,17 +442,17 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) {
   uint32_t ncfgr, bmsr, bmcr, lpa;

 

   AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;

-  (void)phyGet(macp, MII_BMSR);

-  bmsr = phyGet(macp, MII_BMSR);

+  (void)miiGet(macp, MII_BMSR);

+  bmsr = miiGet(macp, MII_BMSR);

   if (!(bmsr & BMSR_LSTATUS)) {

     AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;

     return link_up = FALSE;

   }

 

   ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);

-  bmcr = phyGet(macp, MII_BMCR);

+  bmcr = miiGet(macp, MII_BMCR);

   if (bmcr & BMCR_ANENABLE) {

-    lpa = phyGet(macp, MII_LPA);

+    lpa = miiGet(macp, MII_LPA);

     if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))

       ncfgr |= AT91C_EMAC_SPD;

     if (lpa & (LPA_10FULL | LPA_100FULL))

diff --git a/os/io/platforms/AT91SAM7X/mii_lld.c b/os/io/platforms/AT91SAM7X/mii_lld.c
new file mode 100644
index 000000000..56fd87a51
--- /dev/null
+++ b/os/io/platforms/AT91SAM7X/mii_lld.c
@@ -0,0 +1,115 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file AT91SAM7X/mii_lld.c

+ * @brief AT91SAM7X low level MII driver code

+ * @addtogroup AT91SAM7X_MII

+ * @{

+ */

+

+#include <ch.h>

+#include <mac.h>

+#include <mii.h>

+

+/**

+ * @brief Low level MII driver initialization.

+ */

+void mii_lld_init(void) {

+

+}

+

+/**

+ * @brief Resets a PHY device.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ */

+void mii_lld_reset(MACDriver *macp) {

+

+  /*

+   * Disables the pullups on all the pins that are latched on reset by the PHY.

+   * The status latched into the PHY is:

+   *   PHYADDR  = 00001

+   *   PCS_LPBK = 0 (disabled)

+   *   ISOLATE  = 0 (disabled)

+   *   RMIISEL  = 0 (MII mode)

+   *   RMIIBTB  = 0 (BTB mode disabled)

+   *   SPEED    = 1 (100mbps)

+   *   DUPLEX   = 1 (full duplex)

+   *   ANEG_EN  = 1 (auto negotiation enabled)

+   */

+  AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS;

+

+#ifdef PIOB_PHY_PD_MASK

+  /*

+   * PHY power control.

+   */

+  AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK;       // Becomes an output.

+  AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;     // Default pullup disabled.

+  AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK;      // Output to high level.

+#endif

+

+  /*

+   * PHY reset by pulsing the NRST pin.

+   */

+  AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100;

+  AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;

+  while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))

+    ;

+}

+

+/**

+ * @brief Reads a PHY register through the MII interface.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @return The register value.

+ */

+phyreg_t mii_lld_get(MACDriver *macp, phyaddr_t addr) {

+

+  AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) |            /* SOF */

+                              (0b10 << 28) |            /* RW */

+                              (PHY_ADDRESS << 23) |     /* PHYA */

+                              (addr << 18) |            /* REGA */

+                              (0b10 << 16);             /* CODE */

+  while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))

+    ;

+  return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF);

+}

+

+/**

+ * @brief Writes a PHY register through the MII interface.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @param value the new register value

+ */

+void mii_lld_put(MACDriver *macp, phyaddr_t addr, phyreg_t value) {

+

+  AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) |            /* SOF */

+                              (0b01 << 28) |            /* RW */

+                              (PHY_ADDRESS << 23) |     /* PHYA */

+                              (addr << 18) |            /* REGA */

+                              (0b10 << 16) |            /* CODE */

+                              value;

+  while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))

+    ;

+}

+

+/** @} */

diff --git a/os/io/platforms/AT91SAM7X/mii_lld.h b/os/io/platforms/AT91SAM7X/mii_lld.h
new file mode 100644
index 000000000..f54ee0508
--- /dev/null
+++ b/os/io/platforms/AT91SAM7X/mii_lld.h
@@ -0,0 +1,91 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file AT91SAM7X/mii_lld.h

+ * @brief AT91SAM7X low level MII driver header

+ * @addtogroup AT91SAM7X_MII

+ * @{

+ */

+

+#ifndef _MII_LLD_H_

+#define _MII_LLD_H_

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief PHY manufacturer and model.

+ */

+#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__)

+#define PHY_HARDWARE            PHY_MICREL_KS8721

+#endif

+

+/*===========================================================================*/

+/* PHY specific constants.                                                   */

+/*===========================================================================*/

+

+#define PHY_MICREL_KS8721       0

+

+#if PHY_HARDWARE == PHY_MICREL_KS8721

+#define PHY_ADDRESS             1

+#endif

+

+/**

+ * @brief Pins latched by the PHY at reset.
+ */

+#define PHY_LATCHED_PINS        (AT91C_PB4_ECRS          | AT91C_PB5_ERX0  | \

+                                 AT91C_PB6_ERX1          | AT91C_PB7_ERXER | \

+                                 AT91C_PB13_ERX2         | AT91C_PB14_ERX3 | \

+                                 AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \

+                                 AT91C_PIO_PB26)

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief Type of a PHY register value.

+ */

+typedef uint16_t phyreg_t;

+

+/**

+ * @brief Type of a PHY register address.

+ */

+typedef uint8_t phyaddr_t;

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void mii_lld_init(void);

+  void mii_lld_reset(MACDriver *macp);

+  phyreg_t mii_lld_get(MACDriver *macp, phyaddr_t addr);

+  void mii_lld_put(MACDriver *macp, phyaddr_t addr, phyreg_t value);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _MII_LLD_H_ */

+

+/** @} */

diff --git a/os/io/platforms/AT91SAM7X/platform.dox b/os/io/platforms/AT91SAM7X/platform.dox
index 6176140ad..1e5b7f8c8 100644
--- a/os/io/platforms/AT91SAM7X/platform.dox
+++ b/os/io/platforms/AT91SAM7X/platform.dox
@@ -66,8 +66,19 @@
  */

 

 /**

- * @defgroup AT91SAM7X_EMAC AT91SAM7X EMAC Support

+ * @defgroup AT91SAM7X_MAC AT91SAM7X EMAC Support

  * @brief EMAC peripheral support.

+ * @details the @ref MAC supports the AT91SAM7X EMAC peripheral.

+ *

+ * @ingroup AT91SAM7X

+ */

+

+/**

+ * @defgroup AT91SAM7X_MII AT91SAM7X MII Support

+ * @brief EMAC peripheral support.

+ * @details the @ref MII supports the AT91SAM7X EMAC peripheral communicating

+ *          with an external PHY transceiver. The driver currently supports

+ *          only the Micrel KS8721 PHY module.

  *

  * @ingroup AT91SAM7X

  */

diff --git a/os/io/templates/mii_lld.c b/os/io/templates/mii_lld.c
new file mode 100644
index 000000000..2149ebec3
--- /dev/null
+++ b/os/io/templates/mii_lld.c
@@ -0,0 +1,70 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file templates/mii_lld.c

+ * @brief MII Driver subsystem low level driver source template

+ * @addtogroup MII_LLD

+ * @{

+ */

+

+#include <ch.h>

+#include <mac.h>

+#include <mii.h>

+

+/**

+ * @brief Low level MII driver initialization.

+ */

+void mii_lld_init(void) {

+

+}

+

+/**

+ * Resets a PHY device.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ */

+void mii_lld_reset(MACDriver *macp) {

+

+}

+

+/**

+ * @brief Reads a PHY register through the MII interface.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @return The register value.

+ */

+phyreg_t mii_lld_get(MACDriver *macp, phyaddr_t addr) {

+

+  return 0;

+}

+

+/**

+ * @brief Writes a PHY register through the MII interface.

+ *

+ * @param[in] macp pointer to the @p MACDriver object

+ * @param addr the register address

+ * @param value the new register value

+ */

+void mii_lld_put(MACDriver *macp, phyaddr_t addr, phyreg_t value) {

+

+}

+

+/** @} */

diff --git a/os/io/templates/mii_lld.h b/os/io/templates/mii_lld.h
new file mode 100644
index 000000000..974588363
--- /dev/null
+++ b/os/io/templates/mii_lld.h
@@ -0,0 +1,65 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file templates/mii_lld.h

+ * @brief MII Driver subsystem low level driver header template

+ * @addtogroup MII_LLD

+ * @{

+ */

+

+#ifndef _MII_LLD_H_

+#define _MII_LLD_H_

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief Type of a PHY register value.

+ */

+typedef uint16_t phyreg_t;

+

+/**

+ * @brief Type of a PHY register address.

+ */

+typedef uint8_t phyaddr_t;

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void mii_lld_init(void);

+  void mii_lld_reset(MACDriver *macp);

+  phyreg_t mii_lld_get(MACDriver *macp, phyaddr_t addr);

+  void mii_lld_put(MACDriver *macp, phyaddr_t addr, phyreg_t value);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _MII_LLD_H_ */

+

+/** @} */