Fixed bug #550.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7548 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 53 insertions, 12 deletions

diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
index d61f9a02d..7cc925c70 100644
--- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -134,10 +134,18 @@ void stm32_clock_init(void) {
   RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

   while (!(RCC->CR & RCC_CR_HSIRDY))

     ;                                       /* Wait until HSI is stable.    */

+

+  /* HSI is selected as new source without touching the other fields in

+     CFGR. Clearing the register has to be postponed after HSI is the

+     new source.*/

+  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW */

+  RCC->CFGR |= RCC_CFGR_SWS_HSI;            /* Select HSI as internal*/

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Wait until HSI is selected.  */

+

+  /* Registers finally cleared to reset values.*/

   RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

   RCC->CFGR = 0;                            /* CFGR reset value.            */

-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

-    ;                                       /* Waits until HSI is selected. */

 

 #if STM32_HSE_ENABLED

   /* HSE activation.*/

diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
index 772480d32..e5291aabf 100644
--- a/os/hal/ports/STM32/STM32F1xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
@@ -206,14 +206,23 @@ void stm32_clock_init(void) {
 void stm32_clock_init(void) {

 

 #if !STM32_NO_INIT

-  /* HSI setup.*/

+  /* HSI setup, it enforces the reset situation in order to handle possible

+     problems with JTAG probes and re-initializations.*/

   RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

   while (!(RCC->CR & RCC_CR_HSIRDY))

     ;                                       /* Wait until HSI is stable.    */

-  RCC->CFGR = 0;

-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

+

+  /* HSI is selected as new source without touching the other fields in

+     CFGR. Clearing the register has to be postponed after HSI is the

+     new source.*/

+  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW */

+  RCC->CFGR |= RCC_CFGR_SWS_HSI;            /* Select HSI as internal*/

   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

-    ;                                       /* Wait until HSI is the source.*/

+    ;                                       /* Wait until HSI is selected.  */

+

+  /* Registers finally cleared to reset values.*/

+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

+  RCC->CFGR = 0;                            /* CFGR reset value.            */

 

 #if STM32_HSE_ENABLED

 #if defined(STM32_HSE_BYPASS)

diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c
index b8c3e25be..b0af790a9 100644
--- a/os/hal/ports/STM32/STM32F37x/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -138,10 +138,18 @@ void stm32_clock_init(void) {
   RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

   while (!(RCC->CR & RCC_CR_HSIRDY))

     ;                                       /* Wait until HSI is stable.    */

+

+  /* HSI is selected as new source without touching the other fields in

+     CFGR. Clearing the register has to be postponed after HSI is the

+     new source.*/

+  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW */

+  RCC->CFGR |= RCC_CFGR_SWS_HSI;            /* Select HSI as internal*/

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Wait until HSI is selected.  */

+

+  /* Registers finally cleared to reset values.*/

   RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

   RCC->CFGR = 0;                            /* CFGR reset value.            */

-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

-    ;                                       /* Waits until HSI is selected. */

 

 #if STM32_HSE_ENABLED

   /* HSE activation.*/

diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
index 9c02300dc..97a56f142 100644
--- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -143,10 +143,18 @@ void stm32_clock_init(void) {
   RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

   while (!(RCC->CR & RCC_CR_HSIRDY))

     ;                                       /* Wait until HSI is stable.    */

+

+  /* HSI is selected as new source without touching the other fields in

+     CFGR. Clearing the register has to be postponed after HSI is the

+     new source.*/

+  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW */

+  RCC->CFGR |= RCC_CFGR_SWS_HSI;            /* Select HSI as internal*/

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Wait until HSI is selected.  */

+

+  /* Registers finally cleared to reset values.*/

   RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

   RCC->CFGR = 0;                            /* CFGR reset value.            */

-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

-    ;                                       /* Waits until HSI is selected. */

 

 #if STM32_HSE_ENABLED

   /* HSE activation.*/

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 082fb52a6..92e5b9ec6 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -155,10 +155,18 @@ void stm32_clock_init(void) {
   RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

   while (!(RCC->CR & RCC_CR_HSIRDY))

     ;                                       /* Wait until HSI is stable.    */

+

+  /* HSI is selected as new source without touching the other fields in

+     CFGR. Clearing the register has to be postponed after HSI is the

+     new source.*/

+  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW */

+  RCC->CFGR |= RCC_CFGR_SWS_HSI;            /* Select HSI as internal*/

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Wait until HSI is selected.  */

+

+  /* Registers finally cleared to reset values.*/

   RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

   RCC->CFGR = 0;                            /* CFGR reset value.            */

-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

-    ;                                       /* Waits until HSI is selected. */

 

 #if STM32_HSE_ENABLED

   /* HSE activation.*/