diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32F1xx/hal_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/hal_lld.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c index 772480d32..e5291aabf 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c @@ -206,14 +206,23 @@ void stm32_clock_init(void) { void stm32_clock_init(void) {
#if !STM32_NO_INIT
- /* HSI setup.*/
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
- RCC->CFGR = 0;
- RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+
+ /* HSI is selected as new source without touching the other fields in
+ CFGR. Clearing the register has to be postponed after HSI is the
+ new source.*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
+ RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
- ; /* Wait until HSI is the source.*/
+ ; /* Wait until HSI is selected. */
+
+ /* Registers finally cleared to reset values.*/
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
|