git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5841 35acf78f-673a-0410-8e92-d51de3d6d3f4

6 files changed, 61 insertions, 251 deletions

diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.c b/os/hal/platforms/SPC560Dxx/hal_lld.c
index 5d14daf27..87d2c88fa 100644
--- a/os/hal/platforms/SPC560Dxx/hal_lld.c
+++ b/os/hal/platforms/SPC560Dxx/hal_lld.c
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    SPC560BCxx/hal_lld.c

- * @brief   SPC560B/Cxx HAL subsystem low level driver source.

+ * @file    SPC560Dxx/hal_lld.c

+ * @brief   SPC560Dxx HAL subsystem low level driver source.

  *

  * @addtogroup HAL

  * @{

diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.h b/os/hal/platforms/SPC560Dxx/hal_lld.h
index ddf44dff3..13973ed33 100644
--- a/os/hal/platforms/SPC560Dxx/hal_lld.h
+++ b/os/hal/platforms/SPC560Dxx/hal_lld.h
@@ -15,8 +15,8 @@
 */

 

 /**

- * @file    SPC560BCxx/hal_lld.h

- * @brief   SPC560B/Cxx HAL subsystem low level driver header.

+ * @file    SPC560Dxx/hal_lld.h

+ * @brief   SPC560Dxx HAL subsystem low level driver header.

  * @pre     This module requires the following macros to be defined in the

  *          @p board.h file:

  *          - SPC5_XOSC_CLK.

@@ -30,8 +30,8 @@
 #ifndef _HAL_LLD_H_

 #define _HAL_LLD_H_

 

-#include "xpc560bc.h"

-#include "spc560bc_registry.h"

+#include "xpc560d.h"

+#include "spc560d_registry.h"

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

@@ -46,7 +46,7 @@
  * @name    Platform identification

  * @{

  */

-#define PLATFORM_NAME               "SPC560B/Cxx Car Body and Convenience"

+#define PLATFORM_NAME               "SPC560Dxx Car Body and Convenience"

 /** @} */

 

 /**

@@ -64,16 +64,6 @@
 #define SPC5_XOSC_CLK_MIN           4000000

 

 /**

- * @brief   Maximum SXOSC clock frequency.

- */

-#define SPC5_SXOSC_CLK_MAX          40000

-

-/**

- * @brief   Minimum SXOSC clock frequency.

- */

-#define SPC5_SXOSC_CLK_MIN          32000

-

-/**

  * @brief   Maximum FMPLLs input clock frequency.

  */

 #define SPC5_FMPLLIN_MIN            4000000

@@ -81,7 +71,7 @@
 /**

  * @brief   Maximum FMPLLs input clock frequency.

  */

-#define SPC5_FMPLLIN_MAX            64000000

+#define SPC5_FMPLLIN_MAX            48000000

 

 /**

  * @brief   Maximum FMPLLs VCO clock frequency.

@@ -96,7 +86,7 @@
 /**

  * @brief   Maximum FMPLL0 output clock frequency.

  */

-#define SPC5_FMPLL0_CLK_MAX         64000000

+#define SPC5_FMPLL0_CLK_MAX         48000000

 /** @} */

 

 /**

@@ -247,7 +237,7 @@
 

 /**

  * @brief   FMPLL0 IDF divider value.

- * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.

+ * @note    The default value is calculated for XOSC=8MHz and PHI=48MHz.

  */

 #if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)

 #define SPC5_FMPLL0_IDF_VALUE               1

@@ -255,18 +245,18 @@
 

 /**

  * @brief   FMPLL0 NDIV divider value.

- * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.

+ * @note    The default value is calculated for XOSC=8MHz and PHI=48MHz.

  */

 #if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)

-#define SPC5_FMPLL0_NDIV_VALUE              32

+#define SPC5_FMPLL0_NDIV_VALUE              48

 #endif

 

 /**

  * @brief   FMPLL0 ODF divider value.

- * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.

+ * @note    The default value is calculated for XOSC=8MHz and PHI=48MHz.

  */

 #if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)

-#define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4

+#define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV8

 #endif

 

 /**

@@ -639,7 +629,7 @@
  * Configuration-related checks.

  */

 #if !defined(SPC560BCxx_MCUCONF)

-#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined"

+#error "Using a wrong mcuconf.h file, SPC560Dxx_MCUCONF not defined"

 #endif

 

 /* Check on the XOSC frequency.*/

diff --git a/os/hal/platforms/SPC560Dxx/platform.mk b/os/hal/platforms/SPC560Dxx/platform.mk
index 3432a7b16..6505aa352 100644
--- a/os/hal/platforms/SPC560Dxx/platform.mk
+++ b/os/hal/platforms/SPC560Dxx/platform.mk
@@ -1,11 +1,11 @@
-# List of all the SPC560B/Cxx platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx/hal_lld.c \

+# List of all the SPC560Dxx platform files.

+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c

 

 # Required include directories

-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx \

+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1

diff --git a/os/hal/platforms/SPC560Dxx/spc560d_registry.h b/os/hal/platforms/SPC560Dxx/spc560d_registry.h
index ebcf5fef5..294e6d118 100644
--- a/os/hal/platforms/SPC560Dxx/spc560d_registry.h
+++ b/os/hal/platforms/SPC560Dxx/spc560d_registry.h
@@ -15,26 +15,56 @@
 */

 

 /**

- * @file    SPC560BCxx/spc560bc_registry.h

- * @brief   SPC560B/Cxx capabilities registry.

+ * @file    SPC560Dxx/spc560d_registry.h

+ * @brief   SPC560Dxx capabilities registry.

  *

  * @addtogroup HAL

  * @{

  */

 

-#ifndef _SPC560BC_REGISTRY_H_

-#define _SPC560BC_REGISTRY_H_

+#ifndef _SPC560D_REGISTRY_H_

+#define _SPC560D_REGISTRY_H_

 

 /*===========================================================================*/

 /* Platform capabilities.                                                    */

 /*===========================================================================*/

 

 /**

- * @name    SPC560B/Cxx capabilities

+ * @name    SPC560Dxx capabilities

  * @{

  */

+/* DSPI attribures.*/

+#define SPC5_HAS_DSPI0                      TRUE

+#define SPC5_HAS_DSPI1                      TRUE

+#define SPC5_HAS_DSPI2                      FALSE

+#define SPC5_HAS_DSPI3                      FALSE

+#define SPC5_HAS_DSPI4                      FALSE

+#define SPC5_DSPI_FIFO_DEPTH                4

+#define SPC5_DSPI0_PCTL                     4

+#define SPC5_DSPI1_PCTL                     5

+#define SPC5_DSPI0_TX1_DMA_DEV_ID           1

+#define SPC5_DSPI0_TX2_DMA_DEV_ID           0

+#define SPC5_DSPI0_RX_DMA_DEV_ID            2

+#define SPC5_DSPI1_TX1_DMA_DEV_ID           3

+#define SPC5_DSPI1_TX2_DMA_DEV_ID           0

+#define SPC5_DSPI1_RX_DMA_DEV_ID            4

+#define SPC5_DSPI0_TFFF_HANDLER             vector76

+#define SPC5_DSPI0_TFFF_NUMBER              76

+#define SPC5_DSPI1_TFFF_HANDLER             vector96

+#define SPC5_DSPI1_TFFF_NUMBER              96

+#define SPC5_DSPI0_ENABLE_CLOCK()                                           \

+  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)

+#define SPC5_DSPI0_DISABLE_CLOCK()                                          \

+  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)

+#define SPC5_DSPI1_ENABLE_CLOCK()                                           \

+  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)

+#define SPC5_DSPI1_DISABLE_CLOCK()                                          \

+  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)

+

 /* eDMA attributes.*/

-#define SPC5_HAS_EDMA                       FALSE

+#define SPC5_HAS_EDMA                       TRUE

+#define SPC5_EDMA_NCHANNELS                 16

+#define SPC5_EDMA_HAS_MUX                   TRUE

 

 /* LINFlex attributes.*/

 #define SPC5_HAS_LINFLEX0                   TRUE

@@ -70,16 +100,7 @@
 #define SPC5_LINFLEX2_CLK                   (halSPCGetSystemClock() /       \

                                              SPC5_PERIPHERAL1_CLK_DIV_VALUE)

 

-#define SPC5_HAS_LINFLEX3                   TRUE

-#define SPC5_LINFLEX3_PCTL                  51

-#define SPC5_LINFLEX3_RXI_HANDLER           vector122

-#define SPC5_LINFLEX3_TXI_HANDLER           vector123

-#define SPC5_LINFLEX3_ERR_HANDLER           vector124

-#define SPC5_LINFLEX3_RXI_NUMBER            122

-#define SPC5_LINFLEX3_TXI_NUMBER            123

-#define SPC5_LINFLEX3_ERR_NUMBER            124

-#define SPC5_LINFLEX3_CLK                   (halSPCGetSystemClock() /       \

-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)

+#define SPC5_HAS_LINFLEX3                   FALSE

 

 /* SIUL attributes.*/

 #define SPC5_HAS_SIUL                       TRUE

@@ -88,213 +109,8 @@
 #define SPC5_SIUL_NUM_PCRS                  123

 #define SPC5_SIUL_NUM_PADSELS               32

 #define SPC5_SIUL_SYSTEM_PINS               32,33,121,122

-

-/* eMIOS attributes.*/

-#define SPC5_HAS_EMIOS0                     TRUE

-#define SPC5_EMIOS0_PCTL                    72

-#define SPC5_EMIOS0_GFR_F0F1_HANDLER        vector141

-#define SPC5_EMIOS0_GFR_F2F3_HANDLER        vector142

-#define SPC5_EMIOS0_GFR_F4F5_HANDLER        vector143

-#define SPC5_EMIOS0_GFR_F6F7_HANDLER        vector144

-#define SPC5_EMIOS0_GFR_F8F9_HANDLER        vector145

-#define SPC5_EMIOS0_GFR_F10F11_HANDLER      vector146

-#define SPC5_EMIOS0_GFR_F12F13_HANDLER      vector147

-#define SPC5_EMIOS0_GFR_F14F15_HANDLER      vector148

-#define SPC5_EMIOS0_GFR_F16F17_HANDLER      vector149

-#define SPC5_EMIOS0_GFR_F18F19_HANDLER      vector150

-#define SPC5_EMIOS0_GFR_F20F21_HANDLER      vector151

-#define SPC5_EMIOS0_GFR_F22F23_HANDLER      vector152

-#define SPC5_EMIOS0_GFR_F24F25_HANDLER      vector153

-#define SPC5_EMIOS0_GFR_F26F27_HANDLER      vector154

-#define SPC5_EMIOS0_GFR_F0F1_NUMBER         141

-#define SPC5_EMIOS0_GFR_F2F3_NUMBER         142

-#define SPC5_EMIOS0_GFR_F4F5_NUMBER         143

-#define SPC5_EMIOS0_GFR_F6F7_NUMBER         144

-#define SPC5_EMIOS0_GFR_F8F9_NUMBER         145

-#define SPC5_EMIOS0_GFR_F10F11_NUMBER       146

-#define SPC5_EMIOS0_GFR_F12F13_NUMBER       147

-#define SPC5_EMIOS0_GFR_F14F15_NUMBER       148

-#define SPC5_EMIOS0_GFR_F16F17_NUMBER       149

-#define SPC5_EMIOS0_GFR_F18F19_NUMBER       150

-#define SPC5_EMIOS0_GFR_F20F21_NUMBER       151

-#define SPC5_EMIOS0_GFR_F22F23_NUMBER       152

-#define SPC5_EMIOS0_GFR_F24F25_NUMBER       153

-#define SPC5_EMIOS0_GFR_F26F27_NUMBER       154

-

-#define SPC5_EMIOS0_CLK                     (halSPCGetSystemClock() /         \

-                                             SPC5_PERIPHERAL3_CLK_DIV_VALUE / \

-                                             SPC5_EMIOS0_GLOBAL_PRESCALER)

-

-

-#define SPC5_HAS_EMIOS1                     TRUE

-#define SPC5_EMIOS1_PCTL                    73

-#define SPC5_EMIOS1_GFR_F0F1_HANDLER        vector157

-#define SPC5_EMIOS1_GFR_F2F3_HANDLER        vector158

-#define SPC5_EMIOS1_GFR_F4F5_HANDLER        vector159

-#define SPC5_EMIOS1_GFR_F6F7_HANDLER        vector160

-#define SPC5_EMIOS1_GFR_F8F9_HANDLER        vector161

-#define SPC5_EMIOS1_GFR_F10F11_HANDLER      vector162

-#define SPC5_EMIOS1_GFR_F12F13_HANDLER      vector163

-#define SPC5_EMIOS1_GFR_F14F15_HANDLER      vector164

-#define SPC5_EMIOS1_GFR_F16F17_HANDLER      vector165

-#define SPC5_EMIOS1_GFR_F18F19_HANDLER      vector166

-#define SPC5_EMIOS1_GFR_F20F21_HANDLER      vector167

-#define SPC5_EMIOS1_GFR_F22F23_HANDLER      vector168

-#define SPC5_EMIOS1_GFR_F24F25_HANDLER      vector169

-#define SPC5_EMIOS1_GFR_F26F27_HANDLER      vector170

-#define SPC5_EMIOS1_GFR_F0F1_NUMBER         157

-#define SPC5_EMIOS1_GFR_F2F3_NUMBER         158

-#define SPC5_EMIOS1_GFR_F4F5_NUMBER         159

-#define SPC5_EMIOS1_GFR_F6F7_NUMBER         160

-#define SPC5_EMIOS1_GFR_F8F9_NUMBER         161

-#define SPC5_EMIOS1_GFR_F10F11_NUMBER       162

-#define SPC5_EMIOS1_GFR_F12F13_NUMBER       163

-#define SPC5_EMIOS1_GFR_F14F15_NUMBER       164

-#define SPC5_EMIOS1_GFR_F16F17_NUMBER       165

-#define SPC5_EMIOS1_GFR_F18F19_NUMBER       166

-#define SPC5_EMIOS1_GFR_F20F21_NUMBER       167

-#define SPC5_EMIOS1_GFR_F22F23_NUMBER       168

-#define SPC5_EMIOS1_GFR_F24F25_NUMBER       169

-#define SPC5_EMIOS1_GFR_F26F27_NUMBER       170

-

-#define SPC5_EMIOS1_CLK                     (halSPCGetSystemClock() /         \

-                                             SPC5_PERIPHERAL3_CLK_DIV_VALUE / \

-                                             SPC5_EMIOS1_GLOBAL_PRESCALER)

-

-/* FlexCAN attributes.*/

-#define SPC5_HAS_FLEXCAN0                                   TRUE

-#define SPC5_FLEXCAN0_PCTL                                  16

-#define SPC5_FLEXCAN0_MB                                    64

-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector65

-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector66

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER             vector68

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER             vector69

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER             vector70

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER             vector71

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector72

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER             vector73

-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            65

-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               66

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER              68

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER              69

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER              70

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER              71

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              72

-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER              73

-#define SPC5_FLEXCAN0_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);

-#define SPC5_FLEXCAN0_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);

-

-#define SPC5_HAS_FLEXCAN1                                   TRUE

-#define SPC5_FLEXCAN1_PCTL                                  17

-#define SPC5_FLEXCAN1_MB                                    64

-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER           vector85

-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER              vector86

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER             vector88

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER             vector89

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER             vector90

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER             vector91

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER             vector92

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER             vector93

-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER            85

-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER               86

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER              88

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER              89

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER              90

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER              91

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER              92

-#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER              93

-#define SPC5_FLEXCAN1_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);

-#define SPC5_FLEXCAN1_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);

-

-#define SPC5_HAS_FLEXCAN2                                   TRUE

-#define SPC5_FLEXCAN2_PCTL                                  18

-#define SPC5_FLEXCAN2_MB                                    64

-#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER           vector105

-#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER              vector106

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER             vector108

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER             vector109

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER             vector110

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER             vector111

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER             vector112

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER             vector113

-#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER            105

-#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER               106

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER              108

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER              109

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER              110

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER              111

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER              112

-#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER              113

-#define SPC5_FLEXCAN2_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);

-#define SPC5_FLEXCAN2_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);

-

-#define SPC5_HAS_FLEXCAN3                                   TRUE

-#define SPC5_FLEXCAN3_PCTL                                  19

-#define SPC5_FLEXCAN3_MB                                    64

-#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER           vector173

-#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER              vector174

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER             vector176

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER             vector177

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER             vector178

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER             vector179

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER             vector180

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER             vector181

-#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER            173

-#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER               174

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER              176

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER              177

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER              178

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER              179

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER              180

-#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER              181

-#define SPC5_FLEXCAN3_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);

-#define SPC5_FLEXCAN3_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);

-

-#define SPC5_HAS_FLEXCAN4                                   TRUE

-#define SPC5_FLEXCAN4_PCTL                                  20

-#define SPC5_FLEXCAN4_MB                                    64

-#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER           vector190

-#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER              vector191

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER             vector193

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER             vector194

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER             vector195

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER             vector196

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER             vector197

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER             vector198

-#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER            190

-#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER               191

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER              193

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER              194

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER              195

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER              196

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER              197

-#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER              198

-#define SPC5_FLEXCAN4_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);

-#define SPC5_FLEXCAN4_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);

-

-#define SPC5_HAS_FLEXCAN5                                   TRUE

-#define SPC5_FLEXCAN5_PCTL                                  21

-#define SPC5_FLEXCAN5_MB                                    64

-#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER           vector202

-#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER              vector203

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER             vector205

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER             vector206

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER             vector207

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER             vector208

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER             vector209

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER             vector210

-#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER            202

-#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER               203

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER              205

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER              206

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER              207

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER              208

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER              209

-#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER              210

-#define SPC5_FLEXCAN5_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);

-#define SPC5_FLEXCAN5_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);

 /** @} */

 

-#endif /* _SPC560BC_REGISTRY_H_ */

+#endif /* _SPC560D_REGISTRY_H_ */

 

 /** @} */

diff --git a/os/hal/platforms/SPC560Dxx/typedefs.h b/os/hal/platforms/SPC560Dxx/typedefs.h
index 5ab294e4b..290173872 100644
--- a/os/hal/platforms/SPC560Dxx/typedefs.h
+++ b/os/hal/platforms/SPC560Dxx/typedefs.h
@@ -15,7 +15,7 @@
 */

 

 /**

- * @file    SPC560BCxx/typedefs.h

+ * @file    SPC560Dxx/typedefs.h

  * @brief   Dummy typedefs file.

  */

 

diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
index 18107f065..54d38e0f6 100644
--- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h
+++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
@@ -186,7 +186,11 @@
 /* SIUL attributes.*/

 #define SPC5_HAS_SIUL                       TRUE

 #define SPC5_SIUL_NUM_PORTS                 8

+#if defined(_SPC560PXX_SMALL_)

+#define SPC5_SIUL_NUM_PCRS                  72

+#else

 #define SPC5_SIUL_NUM_PCRS                  108

+#endif

 #define SPC5_SIUL_NUM_PADSELS               36

 

 /* FlexPWM attributes.*/