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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 14:25:39 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 14:25:39 +0000 |
| commit | 8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e (patch) | |
| tree | ca94c78ac5bacf1740e95dd60d8e0f5288056bfe /os/hal | |
| parent | 126943984c591c952bd0b9f6b2d36d97be823de3 (diff) | |
| download | ChibiOS-8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e.tar.gz ChibiOS-8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e.tar.bz2 ChibiOS-8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5849 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/spc560p_registry.h | 15 | ||||
| -rw-r--r-- | os/hal/platforms/SPC564Axx/spc564a_registry.h | 18 | ||||
| -rw-r--r-- | os/hal/platforms/SPC56ELxx/spc56el_registry.h | 9 |
3 files changed, 33 insertions, 9 deletions
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 54d38e0f6..4f528056e 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -93,6 +93,15 @@ #define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_DSPI2_RX_DMA_CH_ID 12
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
@@ -124,6 +133,9 @@ #if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_DSPI3 TRUE
#define SPC5_DSPI3_PCTL 7
+#define SPC5_DSPI3_TX1_DMA_CH_ID 13
+#define SPC5_DSPI3_TX2_DMA_CH_ID 14
+#define SPC5_DSPI3_RX_DMA_CH_ID 15
#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
#define SPC5_DSPI3_RX_DMA_DEV_ID 8
@@ -140,6 +152,9 @@ #if defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_DSPI4 TRUE
#define SPC5_DSPI4_PCTL 8
+#define SPC5_DSPI4_TX1_DMA_CH_ID 1
+#define SPC5_DSPI4_TX2_DMA_CH_ID 2
+#define SPC5_DSPI4_RX_DMA_CH_ID 3
#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
#define SPC5_DSPI4_RX_DMA_DEV_ID 21
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index bcdd6753b..ec584abdf 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -54,15 +54,15 @@ #define SPC5_HAS_DSPI3 TRUE
#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
-#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
-#define SPC5_DSPI1_TX2_DMA_DEV_ID 24
-#define SPC5_DSPI1_RX_DMA_DEV_ID 13
-#define SPC5_DSPI2_TX1_DMA_DEV_ID 14
-#define SPC5_DSPI2_TX2_DMA_DEV_ID 25
-#define SPC5_DSPI2_RX_DMA_DEV_ID 15
-#define SPC5_DSPI3_TX1_DMA_DEV_ID 16
-#define SPC5_DSPI3_TX2_DMA_DEV_ID 26
-#define SPC5_DSPI3_RX_DMA_DEV_ID 17
+#define SPC5_DSPI1_TX1_DMA_CH_ID 12
+#define SPC5_DSPI1_TX2_DMA_CH_ID 24
+#define SPC5_DSPI1_RX_DMA_CH_ID 13
+#define SPC5_DSPI2_TX1_DMA_CH_ID 14
+#define SPC5_DSPI2_TX2_DMA_CH_ID 25
+#define SPC5_DSPI2_RX_DMA_CH_ID 15
+#define SPC5_DSPI3_TX1_DMA_CH_ID 16
+#define SPC5_DSPI3_TX2_DMA_CH_ID 26
+#define SPC5_DSPI3_RX_DMA_CH_ID 17
#define SPC5_DSPI1_EOQF_HANDLER vector132
#define SPC5_DSPI1_EOQF_NUMBER 132
#define SPC5_DSPI1_TFFF_HANDLER vector133
diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h index 83fdab87c..6ab0ae2e2 100644 --- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -48,6 +48,15 @@ #define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_DSPI2_RX_DMA_CH_ID 12
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
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