diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-27 13:42:33 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-27 13:42:33 +0000 |
| commit | 2b01d72e42576594924aa12fe50571cd56cafbb5 (patch) | |
| tree | d45beff58f2f862917cb11ad053c97c8f313779f /os/hal | |
| parent | 0bc6e6f77fced2bf8db588eb765c78bbf7cf0f20 (diff) | |
| download | ChibiOS-2b01d72e42576594924aa12fe50571cd56cafbb5.tar.gz ChibiOS-2b01d72e42576594924aa12fe50571cd56cafbb5.tar.bz2 ChibiOS-2b01d72e42576594924aa12fe50571cd56cafbb5.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4242 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32F0xx/adc_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F0xx/adc_lld.h | 26 |
2 files changed, 19 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c index 51905c3d4..af03bd058 100644 --- a/os/hal/platforms/STM32F0xx/adc_lld.c +++ b/os/hal/platforms/STM32F0xx/adc_lld.c @@ -102,7 +102,7 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { *
* @isr
*/
-CH_IRQ_HANDLER(ADC1_IRQHandler) {
+CH_IRQ_HANDLER(ADC1_COMP_IRQHandler) {
uint32_t isr;
CH_IRQ_PROLOGUE();
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h index eeeda1979..dce0d7d1a 100644 --- a/os/hal/platforms/STM32F0xx/adc_lld.h +++ b/os/hal/platforms/STM32F0xx/adc_lld.h @@ -39,14 +39,24 @@ * @name Sampling rates
* @{
*/
-#define ADC_SAMPLE_1P5 0 /**< @brief 14 cycles conversion time */
-#define ADC_SAMPLE_7P5 1 /**< @brief 21 cycles conversion time. */
-#define ADC_SAMPLE_13P5 2 /**< @brief 28 cycles conversion time. */
-#define ADC_SAMPLE_28P5 3 /**< @brief 41 cycles conversion time. */
-#define ADC_SAMPLE_41P5 4 /**< @brief 54 cycles conversion time. */
-#define ADC_SAMPLE_55P5 5 /**< @brief 68 cycles conversion time. */
-#define ADC_SAMPLE_71P5 6 /**< @brief 84 cycles conversion time. */
-#define ADC_SAMPLE_239P5 7 /**< @brief 252 cycles conversion time. */
+#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
+#define ADC_SMPR_SMP_7P5 1 /**< @brief 21 cycles conversion time. */
+#define ADC_SMPR_SMP_13P5 2 /**< @brief 28 cycles conversion time. */
+#define ADC_SMPR_SMP_28P5 3 /**< @brief 41 cycles conversion time. */
+#define ADC_SMPR_SMP_41P5 4 /**< @brief 54 cycles conversion time. */
+#define ADC_SMPR_SMP_55P5 5 /**< @brief 68 cycles conversion time. */
+#define ADC_SMPR_SMP_71P5 6 /**< @brief 84 cycles conversion time. */
+#define ADC_SMPR_SMP_239P5 7 /**< @brief 252 cycles conversion time. */
+/** @} */
+
+/**
+ * @name Resolution
+ * @{
+ */
+#define ADC_CFGR1_RES_12BIT (0 << 3)
+#define ADC_CFGR1_RES_10BIT (1 << 3)
+#define ADC_CFGR1_RES_8BIT (2 << 3)
+#define ADC_CFGR1_RES_6BIT (3 << 3)
/** @} */
/*===========================================================================*/
|