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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-08-23 09:17:33 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-08-23 09:17:33 +0000
commit19745e5d5857dad5ed80ad3465434a9cfc5f5b65 (patch)
treeeb02b2c5fe99c7fe3319fc14e3cd1a20fbbbb025 /os/hal
parent32c2d2fca06f0cc2122a5fc944716b629f8f8fcd (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6208 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
-rw-r--r--os/hal/platforms/STM32F4xx/ext_lld_isr.c128
1 files changed, 57 insertions, 71 deletions
diff --git a/os/hal/platforms/STM32F4xx/ext_lld_isr.c b/os/hal/platforms/STM32F4xx/ext_lld_isr.c
index c99948904..dd1491557 100644
--- a/os/hal/platforms/STM32F4xx/ext_lld_isr.c
+++ b/os/hal/platforms/STM32F4xx/ext_lld_isr.c
@@ -53,14 +53,14 @@
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector58) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -68,14 +68,14 @@ CH_IRQ_HANDLER(EXTI0_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector5C) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -83,14 +83,14 @@ CH_IRQ_HANDLER(EXTI1_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector60) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -98,14 +98,14 @@ CH_IRQ_HANDLER(EXTI2_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector64) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -113,14 +113,14 @@ CH_IRQ_HANDLER(EXTI3_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector68) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -128,10 +128,10 @@ CH_IRQ_HANDLER(EXTI4_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector9C) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
@@ -146,7 +146,7 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -154,10 +154,10 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE0) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
@@ -175,7 +175,7 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -183,29 +183,29 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(PVD_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector44) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
- * @brief EXTI[17] interrupt handler (RTC).
+ * @brief EXTI[17] interrupt handler (RTC_ALARM).
*
* @isr
*/
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE4) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -213,14 +213,14 @@ CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(VectorE8) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -228,14 +228,14 @@ CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector138) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -243,14 +243,14 @@ CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector170) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -258,14 +258,14 @@ CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector48) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 21);
EXTD1.config->channels[21].cb(&EXTD1, 21);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -273,14 +273,14 @@ CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
*
* @isr
*/
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(Vector4C) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 22);
EXTD1.config->channels[22].cb(&EXTD1, 22);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -294,34 +294,20 @@ CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
*/
void ext_lld_exti_irq_enable(void) {
- nvicEnableVector(EXTI0_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
- nvicEnableVector(EXTI1_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
- nvicEnableVector(EXTI2_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
- nvicEnableVector(EXTI3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
- nvicEnableVector(EXTI4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
- nvicEnableVector(EXTI9_5_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
- nvicEnableVector(EXTI15_10_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
- nvicEnableVector(PVD_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
- nvicEnableVector(RTC_Alarm_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
- nvicEnableVector(OTG_FS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
- nvicEnableVector(ETH_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
- nvicEnableVector(OTG_HS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
- nvicEnableVector(TAMP_STAMP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
- nvicEnableVector(RTC_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+ nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+ nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY);
}
/**