git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6207 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 65 insertions, 69 deletions

diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index 52f326648..724dc2938 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -107,10 +107,10 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {

+OSAL_IRQ_HANDLER(ADC1_2_3_IRQHandler) {

   uint32_t sr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

 #if STM32_ADC_USE_ADC1

   sr = ADC1->SR;

@@ -154,7 +154,7 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
   /* TODO: Add here analog watchdog handling.*/

 #endif /* STM32_ADC_USE_ADC3 */

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -210,7 +210,7 @@ void adc_lld_init(void) {
 

   /* The shared vector is initialized on driver initialization and never

      disabled.*/

-  nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));

+  nvicEnableVector(ADC_IRQn, STM32_ADC_IRQ_PRIORITY);

 }

 

 /**

@@ -226,12 +226,12 @@ void adc_lld_start(ADCDriver *adcp) {
   if (adcp->state == ADC_STOP) {

 #if STM32_ADC_USE_ADC1

     if (&ADCD1 == adcp) {

-      bool_t b;

+      bool b;

       b = dmaStreamAllocate(adcp->dmastp,

                             STM32_ADC_ADC1_DMA_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,

                             (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);

       rccEnableADC1(FALSE);

     }

@@ -239,12 +239,12 @@ void adc_lld_start(ADCDriver *adcp) {
 

 #if STM32_ADC_USE_ADC2

     if (&ADCD2 == adcp) {

-      bool_t b;

+      bool b;

       b = dmaStreamAllocate(adcp->dmastp,

                             STM32_ADC_ADC2_DMA_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,

                             (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);

       rccEnableADC2(FALSE);

     }

@@ -252,12 +252,12 @@ void adc_lld_start(ADCDriver *adcp) {
 

 #if STM32_ADC_USE_ADC3

     if (&ADCD3 == adcp) {

-      bool_t b;

+      bool b;

       b = dmaStreamAllocate(adcp->dmastp,

                             STM32_ADC_ADC3_DMA_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,

                             (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);

       rccEnableADC3(FALSE);

     }

diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h
index 7cda791ac..c8f0570eb 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.h
+++ b/os/hal/platforms/STM32F4xx/adc_lld.h
@@ -437,17 +437,13 @@ struct ADCDriver {
   /**

    * @brief Waiting thread.

    */

-  Thread                    *thread;

+  thread_reference_t        thread;

 #endif

 #if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)

-#if CH_USE_MUTEXES || defined(__DOXYGEN__)

   /**

    * @brief Mutex protecting the peripheral.

    */

-  Mutex                     mutex;

-#elif CH_USE_SEMAPHORES

-  Semaphore                 semaphore;

-#endif

+  mutex_t                   mutex;

 #endif /* ADC_USE_MUTUAL_EXCLUSION */

 #if defined(ADC_DRIVER_EXT_FIELDS)

   ADC_DRIVER_EXT_FIELDS

diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c
index 6850901b2..a3bb26b0d 100644
--- a/os/hal/platforms/STM32F4xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F4xx/stm32_dma.c
@@ -124,17 +124,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector6C) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;

   DMA1->LIFCR = STM32_DMA_ISR_MASK << 0;

   if (dma_isr_redir[0].dma_func)

     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -142,17 +142,17 @@ CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector70) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;

   DMA1->LIFCR = STM32_DMA_ISR_MASK << 6;

   if (dma_isr_redir[1].dma_func)

     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -160,17 +160,17 @@ CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector74) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;

   DMA1->LIFCR = STM32_DMA_ISR_MASK << 16;

   if (dma_isr_redir[2].dma_func)

     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -178,17 +178,17 @@ CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector78) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;

   DMA1->LIFCR = STM32_DMA_ISR_MASK << 22;

   if (dma_isr_redir[3].dma_func)

     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -196,17 +196,17 @@ CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector7C) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;

   DMA1->HIFCR = STM32_DMA_ISR_MASK << 0;

   if (dma_isr_redir[4].dma_func)

     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -214,17 +214,17 @@ CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector80) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;

   DMA1->HIFCR = STM32_DMA_ISR_MASK << 6;

   if (dma_isr_redir[5].dma_func)

     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -232,17 +232,17 @@ CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector84) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;

   DMA1->HIFCR = STM32_DMA_ISR_MASK << 16;

   if (dma_isr_redir[6].dma_func)

     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -250,17 +250,17 @@ CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {

+OSAL_IRQ_HANDLER(VectorFC) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;

   DMA1->HIFCR = STM32_DMA_ISR_MASK << 22;

   if (dma_isr_redir[7].dma_func)

     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -268,17 +268,17 @@ CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector120) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;

   DMA2->LIFCR = STM32_DMA_ISR_MASK << 0;

   if (dma_isr_redir[8].dma_func)

     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -286,17 +286,17 @@ CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector124) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;

   DMA2->LIFCR = STM32_DMA_ISR_MASK << 6;

   if (dma_isr_redir[9].dma_func)

     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -304,17 +304,17 @@ CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector128) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;

   DMA2->LIFCR = STM32_DMA_ISR_MASK << 16;

   if (dma_isr_redir[10].dma_func)

     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -322,17 +322,17 @@ CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector12C) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;

   DMA2->LIFCR = STM32_DMA_ISR_MASK << 22;

   if (dma_isr_redir[11].dma_func)

     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -340,17 +340,17 @@ CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector130) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;

   DMA2->HIFCR = STM32_DMA_ISR_MASK << 0;

   if (dma_isr_redir[12].dma_func)

     dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -358,17 +358,17 @@ CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector150) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;

   DMA2->HIFCR = STM32_DMA_ISR_MASK << 6;

   if (dma_isr_redir[13].dma_func)

     dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -376,17 +376,17 @@ CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector154) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;

   DMA2->HIFCR = STM32_DMA_ISR_MASK << 16;

   if (dma_isr_redir[14].dma_func)

     dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -394,17 +394,17 @@ CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {

+OSAL_IRQ_HANDLER(Vector158) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;

   DMA2->HIFCR = STM32_DMA_ISR_MASK << 22;

   if (dma_isr_redir[15].dma_func)

     dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /*===========================================================================*/

@@ -459,7 +459,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
                          stm32_dmaisr_t func,

                          void *param) {

 

-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");

+  osalDbgCheck(dmastp != NULL);

 

   /* Checks if the stream is already taken.*/

   if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)

@@ -483,7 +483,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
 

   /* Enables the associated IRQ vector if a callback is defined.*/

   if (func != NULL)

-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));

+    nvicEnableVector(dmastp->vector, priority);

 

   return FALSE;

 }

@@ -503,11 +503,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
  */

 void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {

 

-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");

+  osalDbgCheck(dmastp != NULL);

 

   /* Check if the streams is not taken.*/

-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,

-              "dmaStreamRelease(), #1", "not allocated");

+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,

+                "not allocated");

 

   /* Disables the associated IRQ vector.*/

   nvicDisableVector(dmastp->vector);