git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6440 35acf78f-673a-0410-8e92-d51de3d6d3f4

7 files changed, 276 insertions, 99 deletions

diff --git a/os/hal/ports/STM32/OTGv1/usb_lld.c b/os/hal/ports/STM32/OTGv1/usb_lld.c
index 8ac1db535..a6197feb8 100644
--- a/os/hal/ports/STM32/OTGv1/usb_lld.c
+++ b/os/hal/ports/STM32/OTGv1/usb_lld.c
@@ -112,14 +112,14 @@ static const stm32_otg_params_t hsparams = {
 static void otg_core_reset(USBDriver *usbp) {

   stm32_otg_t *otgp = usbp->otg;

 

-  halPolledDelay(32);

+  osalSysPolledDelayX(32);

 

   /* Core reset and delay of at least 3 PHY cycles.*/

   otgp->GRSTCTL = GRSTCTL_CSRST;

   while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)

     ;

 

-  halPolledDelay(12);

+  osalSysPolledDelayX(12);

 

   /* Wait AHB idle condition.*/

   while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)

diff --git a/os/hal/ports/STM32F0xx/hal_lld.c b/os/hal/ports/STM32F0xx/hal_lld.c
index 09ab62923..9b6a85b91 100644
--- a/os/hal/ports/STM32F0xx/hal_lld.c
+++ b/os/hal/ports/STM32F0xx/hal_lld.c
@@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) {
 #if STM32_LSE_ENABLED

 #if defined(STM32_LSE_BYPASS)

   /* LSE Bypass.*/

-  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

 #else

   /* No LSE Bypass.*/

-  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;

+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;

 #endif

   while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

     ;                                     /* Waits until LSE is stable.   */

diff --git a/os/hal/ports/STM32F30x/hal_lld.c b/os/hal/ports/STM32F30x/hal_lld.c
index 4521231d5..46561dc76 100644
--- a/os/hal/ports/STM32F30x/hal_lld.c
+++ b/os/hal/ports/STM32F30x/hal_lld.c
@@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) {
 #if STM32_LSE_ENABLED

 #if defined(STM32_LSE_BYPASS)

   /* LSE Bypass.*/

-  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

 #else

   /* No LSE Bypass.*/

-  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;

+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;

 #endif

   while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

     ;                                     /* Waits until LSE is stable.   */

diff --git a/os/hal/ports/STM32F37x/hal_lld.c b/os/hal/ports/STM32F37x/hal_lld.c
index 6234137b0..a34b11546 100644
--- a/os/hal/ports/STM32F37x/hal_lld.c
+++ b/os/hal/ports/STM32F37x/hal_lld.c
@@ -61,10 +61,10 @@ static void hal_lld_backup_domain_init(void) {
 #if STM32_LSE_ENABLED

 #if defined(STM32_LSE_BYPASS)

   /* LSE Bypass.*/

-  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

 #else

   /* No LSE Bypass.*/

-  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;

+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;

 #endif

   while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

     ;                                     /* Waits until LSE is stable.   */

diff --git a/os/hal/ports/STM32F4xx/hal_lld.c b/os/hal/ports/STM32F4xx/hal_lld.c
index e414043cc..7aeb67297 100644
--- a/os/hal/ports/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32F4xx/hal_lld.c
@@ -22,8 +22,6 @@
  * @{

  */

 

-/* TODO: LSEBYP like in F3.*/

-

 #include "hal.h"

 

 /*===========================================================================*/

@@ -60,7 +58,13 @@ static void hal_lld_backup_domain_init(void) {
   }

 

 #if STM32_LSE_ENABLED

+#if defined(STM32_LSE_BYPASS)

+  /* LSE Bypass.*/

+  RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

+#else

+  /* No LSE Bypass.*/

   RCC->BDCR |= RCC_BDCR_LSEON;

+#endif

   while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

     ;                                       /* Waits until LSE is stable.   */

 #endif

@@ -142,17 +146,19 @@ void stm32_clock_init(void) {
   /* PWR initialization.*/

 #if defined(STM32F4XX) || defined(__DOXYGEN__)

   PWR->CR = STM32_VOS;

-  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)

-    ;                           /* Waits until power regulator is stable.   */

 #else

   PWR->CR = 0;

 #endif

 

-  /* Initial clocks setup and wait for HSI stabilization, the MSI clock is

-     always enabled because it is the fallback clock when PLL the fails.*/

-  RCC->CR |= RCC_CR_HSION;

-  while ((RCC->CR & RCC_CR_HSIRDY) == 0)

-    ;                           /* Waits until HSI is stable.               */

+  /* HSI setup, it enforces the reset situation in order to handle possible

+     problems with JTAG probes and re-initializations.*/

+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

+  while (!(RCC->CR & RCC_CR_HSIRDY))

+    ;                                       /* Wait until HSI is stable.    */

+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

+  RCC->CFGR = 0;                            /* CFGR reset value.            */

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Waits until HSI is selected. */

 

 #if STM32_HSE_ENABLED

   /* HSE activation.*/

@@ -179,21 +185,42 @@ void stm32_clock_init(void) {
   RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |

                  STM32_PLLM;

   RCC->CR |= RCC_CR_PLLON;

+

+  /* Synchronization with voltage regulator stabilization.*/

+#if defined(STM32F4XX)

+  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)

+    ;                           /* Waits until power regulator is stable.   */

+

+#if STM32_OVERDRIVE_REQUIRED

+  /* Overdrive activation performed after activating the PLL in order to save

+     time as recommended in RM in "Entering Over-drive mode" paragraph.*/

+  PWR->CR |= PWR_CR_ODEN;

+  while (!(PWR->CSR & PWR_CSR_ODRDY))

+      ;

+  PWR->CR |= PWR_CR_ODSWEN;

+  while (!(PWR->CSR & PWR_CSR_ODSWRDY))

+      ;

+#endif /* STM32_OVERDRIVE_REQUIRED */

+#endif /* defined(STM32F4XX) */

+

+  /* Waiting for PLL lock.*/

   while (!(RCC->CR & RCC_CR_PLLRDY))

-    ;                           /* Waits until PLL is stable.               */

-#endif

+    ;

+#endif /* STM32_OVERDRIVE_REQUIRED */

 

 #if STM32_ACTIVATE_PLLI2S

   /* PLLI2S activation.*/

   RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;

   RCC->CR |= RCC_CR_PLLI2SON;

+

+  /* Waiting for PLL lock.*/

   while (!(RCC->CR & RCC_CR_PLLI2SRDY))

-    ;                           /* Waits until PLLI2S is stable.            */

+    ;

 #endif

 

   /* Other clock-related settings (dividers, MCO etc).*/

-  RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

-               STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;

+  RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

+              STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;

 

   /* Flash setup.*/

 #if defined(STM32_USE_REVISION_A_FIX)

diff --git a/os/hal/ports/STM32F4xx/hal_lld.h b/os/hal/ports/STM32F4xx/hal_lld.h
index 98bc2105c..546914742 100644
--- a/os/hal/ports/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32F4xx/hal_lld.h
@@ -20,14 +20,17 @@
  * @pre     This module requires the following macros to be defined in the

  *          @p board.h file:

  *          - STM32_LSECLK.

+ *          - STM32_LSE_BYPASS (optionally).

  *          - STM32_HSECLK.

  *          - STM32_HSE_BYPASS (optionally).

  *          - STM32_VDD (as hundredths of Volt).

  *          .

  *          One of the following macros must also be defined:

  *          - STM32F2XX for High-performance STM32 F-2 devices.

- *          - STM32F40XX for High-performance STM32 F-4 devices.

- *          - STM32F42XX for High-performance STM32 F-4 devices.

+ *          - STM32F401xx for High-performance STM32 F-4 devices.

+ *          - STM32F40_41xxx for High-performance STM32 F-4 devices.

+ *          - STM32F427_437xx for High-performance STM32 F-4 devices.

+ *          - STM32F429_439xx for High-performance STM32 F-4 devices.

  *          .

  *

  * @addtogroup HAL

@@ -44,37 +47,77 @@
 /*===========================================================================*/

 

 /**

- * @name    Platform identification

+ * @brief   Defines the support for realtime counters in the HAL.

+ */

+#define HAL_IMPLEMENTS_COUNTERS TRUE

+

+/**

+ * @name    Platform identification macros

  * @{

  */

-#if defined(STM32F40XX) || defined(__DOXYGEN__)

-#define PLATFORM_NAME           "STM32F40x/STM32F41x High Performance"

-#elif defined(STM32F42XX)

-#define PLATFORM_NAME           "STM32F42x/STM32F43x High Performance"

-#else /* !defined(STM32F40XX) */

+#if defined(STM32F429_439xx) || defined(__DOXYGEN__)

+#define PLATFORM_NAME           "STM32F429/F439 High Performance with DSP and FPU"

+#define STM32F4XX

+#elif defined(STM32F427_437xx) || defined(__DOXYGEN__)

+#define PLATFORM_NAME           "STM32F427/F437 High Performance with DSP and FPU"

+#define STM32F4XX

+#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)

+#define PLATFORM_NAME           "STM32F407/F417 High Performance with DSP and FPU"

+#define STM32F4XX

+#elif defined(STM32F401xx) || defined(__DOXYGEN__)

+#define PLATFORM_NAME           "STM32F401 High Performance with DSP and FPU"

+#define STM32F4XX

+#elif defined(STM32F2XX) || defined(__DOXYGEN__)

 #define PLATFORM_NAME           "STM32F2xx High Performance"

-#endif /* !defined(STM32F40XX) */

+#else

+#error "STM32F2xx/F4xx device not specified"

+#endif

 /** @} */

 

 /**

  * @name    Absolute Maximum Ratings

  * @{

  */

-#if defined(STM32F40XX) || defined(__DOXYGEN__)

+/**

+ * @name    Absolute Maximum Ratings

+ * @{

+ */

+#if defined(STM32F429_439xx) || defined(STM32F429_439xx) ||                 \

+    defined(__DOXYGEN__)

+/**

+ * @brief   Absolute maximum system clock.

+ */

+#define STM32_SYSCLK_MAX        180000000

+

 /**

  * @brief   Maximum HSE clock frequency.

  */

 #define STM32_HSECLK_MAX        26000000

 

 /**

+ * @brief   Maximum HSE clock frequency using an external source.

+ */

+#define STM32_HSECLK_BYP_MAX    50000000

+

+/**

  * @brief   Minimum HSE clock frequency.

  */

-#define STM32_HSECLK_MIN        1000000

+#define STM32_HSECLK_MIN        4000000

+

+/**

+ * @brief   Minimum HSE clock frequency.

+ */

+#define STM32_HSECLK_BYP_MIN    1000000

 

 /**

  * @brief   Maximum LSE clock frequency.

  */

-#define STM32_LSECLK_MAX        1000000

+#define STM32_LSECLK_MAX        32768

+

+/**

+ * @brief   Maximum LSE clock frequency.

+ */

+#define STM32_LSECLK_BYP_MAX    1000000

 

 /**

  * @brief   Minimum LSE clock frequency.

@@ -84,7 +127,7 @@
 /**

  * @brief   Maximum PLLs input clock frequency.

  */

-#define STM32_PLLIN_MAX         2000000

+#define STM32_PLLIN_MAX         2100000

 

 /**

  * @brief   Minimum PLLs input clock frequency.

@@ -104,7 +147,7 @@
 /**

  * @brief   Maximum PLL output clock frequency.

  */

-#define STM32_PLLOUT_MAX        168000000

+#define STM32_PLLOUT_MAX        180000000

 

 /**

  * @brief   Minimum PLL output clock frequency.

@@ -114,23 +157,67 @@
 /**

  * @brief   Maximum APB1 clock frequency.

  */

-#define STM32_PCLK1_MAX         42000000

+#define STM32_PCLK1_MAX         (STM32_PLLOUT_MAX /4)

 

 /**

  * @brief   Maximum APB2 clock frequency.

  */

-#define STM32_PCLK2_MAX         84000000

+#define STM32_PCLK2_MAX         (STM32_PLLOUT_MAX / 2)

 

 /**

  * @brief   Maximum SPI/I2S clock frequency.

  */

-#define STM32_SPII2S_MAX        37500000

+#define STM32_SPII2S_MAX        45000000

+#endif /* STM32F40_41xxx */

+

+#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)

+#define STM32_SYSCLK_MAX        168000000

+#define STM32_HSECLK_MAX        26000000

+#define STM32_HSECLK_BYP_MAX    50000000

+#define STM32_HSECLK_MIN        4000000

+#define STM32_HSECLK_BYP_MIN    1000000

+#define STM32_LSECLK_MAX        32768

+#define STM32_LSECLK_BYP_MAX    1000000

+#define STM32_LSECLK_MIN        32768

+#define STM32_PLLIN_MAX         2100000

+#define STM32_PLLIN_MIN         950000

+#define STM32_PLLVCO_MAX        432000000

+#define STM32_PLLVCO_MIN        192000000

+#define STM32_PLLOUT_MAX        168000000

+#define STM32_PLLOUT_MIN        24000000

+#define STM32_PCLK1_MAX         42000000

+#define STM32_PCLK2_MAX         84000000

+#define STM32_SPII2S_MAX        42000000

+#endif /* STM32F40_41xxx */

+

+#if defined(STM32F401xx) || defined(__DOXYGEN__)

+#define STM32_SYSCLK_MAX        84000000

+#define STM32_HSECLK_MAX        26000000

+#define STM32_HSECLK_BYP_MAX    50000000

+#define STM32_HSECLK_MIN        4000000

+#define STM32_HSECLK_BYP_MIN    1000000

+#define STM32_LSECLK_MAX        32768

+#define STM32_LSECLK_BYP_MAX    1000000

+#define STM32_LSECLK_MIN        32768

+#define STM32_PLLIN_MAX         2100000

+#define STM32_PLLIN_MIN         950000

+#define STM32_PLLVCO_MAX        432000000

+#define STM32_PLLVCO_MIN        192000000

+#define STM32_PLLOUT_MAX        84000000

+#define STM32_PLLOUT_MIN        24000000

+#define STM32_PCLK1_MAX         42000000

+#define STM32_PCLK2_MAX         84000000

+#define STM32_SPII2S_MAX        42000000

+#endif /* STM32F40_41xxx */

 

-#else /* !defined(STM32F40XX) */

+#if defined(STM32F2XX)

 #define STM32_SYSCLK_MAX        120000000

 #define STM32_HSECLK_MAX        26000000

+#define STM32_HSECLK_BYP_MAX    26000000

 #define STM32_HSECLK_MIN        1000000

-#define STM32_LSECLK_MAX        1000000

+#define STM32_HSECLK_BYP_MIN    1000000

+#define STM32_LSECLK_MAX        32768

+#define STM32_LSECLK_BYP_MAX    1000000

 #define STM32_LSECLK_MIN        32768

 #define STM32_PLLIN_MAX         2000000

 #define STM32_PLLIN_MIN         950000

@@ -140,8 +227,8 @@
 #define STM32_PLLOUT_MIN        24000000

 #define STM32_PCLK1_MAX         30000000

 #define STM32_PCLK2_MAX         60000000

-#define STM32_SPII2S_MAX        37500000

-#endif /* !defined(STM32F40XX) */

+#define STM32_SPII2S_MAX        30000000

+#endif /* defined(STM32F2XX) */

 /** @} */

 

 /**

@@ -156,11 +243,9 @@
  * @name    PWR_CR register bits definitions

  * @{

  */

-#if defined(STM32F40XX) || defined(__DOXYGEN__)

-#define STM32_VOS_MASK          (1 << 14)   /**< Core voltage mask.         */

-#define STM32_VOS_LOW           (0 << 14)   /**< Core voltage set to low.   */

-#define STM32_VOS_HIGH          (1 << 14)   /**< Core voltage set to high.  */

-#endif

+#define STM32_VOS_SCALE3        (PWR_CR_VOS_0)

+#define STM32_VOS_SCALE2        (PWR_CR_VOS_1)

+#define STM32_VOS_SCALE1        (PWR_CR_VOS_1 | PWR_CR_VOS_0)

 #define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */

 #define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */

 #define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */

@@ -307,6 +392,13 @@
 #endif

 

 /**

+ * @brief   Enables the backup RAM regulator.

+ */

+#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)

+#define STM32_BKPRAM_ENABLE         FALSE

+#endif

+

+/**

  * @brief   Enables or disables the HSI clock source.

  */

 #if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)

@@ -352,17 +444,7 @@
 #define STM32_SW                    STM32_SW_PLL

 #endif

 

-#if defined(STM32F40XX) || defined(__DOXYGEN__)

-/**

- * @brief   Core voltage selection.

- * @note    This setting affects all the performance and clock related

- *          settings, the maximum performance is only obtainable selecting

- *          the maximum voltage.

- */

-#if !defined(STM32_VOS) || defined(__DOXYGEN__)

-#define STM32_VOS                   STM32_VOS_HIGH

-#endif

-

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 /**

  * @brief   Clock source for the PLLs.

  * @note    This setting has only effect if the PLL is selected as the

@@ -414,7 +496,7 @@
 #define STM32_PLLQ_VALUE            7

 #endif

 

-#else /* !defined(STM32F40XX) */

+#else /* !defined(STM32F4XX) */

 /**

  * @brief   Clock source for the PLLs.

  * @note    This setting has only effect if the PLL is selected as the

@@ -465,7 +547,7 @@
 #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)

 #define STM32_PLLQ_VALUE            5

 #endif

-#endif /* !defined(STM32F40XX) */

+#endif /* !defined(STM32F4XX) */

 

 /**

  * @brief   AHB prescaler value.

@@ -562,14 +644,7 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-/*

- * MCU variant check.

- */

-#if defined(STM32F42XX)

-#error "unsupported STM32F4XX variant"

-#endif

-

-#if defined(STM32F40XX) || defined(__DOXYGEN__)

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 /*

  * Configuration-related checks.

  */

@@ -577,39 +652,31 @@
 #error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"

 #endif

 

-/**

- * @brief   Maximum SYSCLK.

- * @note    It is a function of the core voltage setting.

- */

-#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__)

-#define STM32_SYSCLK_MAX            168000000

-#else

-#define STM32_SYSCLK_MAX            144000000

-#endif

-

-#else /* !defined(STM32F40XX) */

+#else /* !defined(STM32F4XX) */

 /*

  * Configuration-related checks.

  */

 #if !defined(STM32F2xx_MCUCONF)

 #error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"

 #endif

-#endif /* !defined(STM32F40XX) */

+#endif /* !defined(STM32F4XX) */

 

 /**

  * @brief   Maximum frequency thresholds and wait states for flash access.

  * @note    The values are valid for 2.7V to 3.6V supply range.

  */

-#if defined(STM32F40XX) || defined(__DOXYGEN__)

+#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \

+    defined(STM32F40_41xxx) || defined(__DOXYGEN__)

 #if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)

 #define STM32_0WS_THRESHOLD         30000000

 #define STM32_1WS_THRESHOLD         60000000

 #define STM32_2WS_THRESHOLD         90000000

 #define STM32_3WS_THRESHOLD         120000000

 #define STM32_4WS_THRESHOLD         150000000

-#define STM32_5WS_THRESHOLD         168000000

+#define STM32_5WS_THRESHOLD         180000000

 #define STM32_6WS_THRESHOLD         0

 #define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

 #elif (STM32_VDD >= 240) && (STM32_VDD < 270)

 #define STM32_0WS_THRESHOLD         24000000

 #define STM32_1WS_THRESHOLD         48000000

@@ -618,31 +685,79 @@
 #define STM32_4WS_THRESHOLD         120000000

 #define STM32_5WS_THRESHOLD         144000000

 #define STM32_6WS_THRESHOLD         168000000

+#define STM32_7WS_THRESHOLD         180000000

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

+#define STM32_0WS_THRESHOLD         22000000

+#define STM32_1WS_THRESHOLD         44000000

+#define STM32_2WS_THRESHOLD         66000000

+#define STM32_3WS_THRESHOLD         88000000

+#define STM32_4WS_THRESHOLD         110000000

+#define STM32_5WS_THRESHOLD         132000000

+#define STM32_6WS_THRESHOLD         154000000

+#define STM32_7WS_THRESHOLD         176000000

+#define STM32_8WS_THRESHOLD         180000000

+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

+#define STM32_0WS_THRESHOLD         20000000

+#define STM32_1WS_THRESHOLD         40000000

+#define STM32_2WS_THRESHOLD         60000000

+#define STM32_3WS_THRESHOLD         80000000

+#define STM32_4WS_THRESHOLD         100000000

+#define STM32_5WS_THRESHOLD         120000000

+#define STM32_6WS_THRESHOLD         140000000

+#define STM32_7WS_THRESHOLD         168000000

+#define STM32_8WS_THRESHOLD         0

+#else

+#error "invalid VDD voltage specified"

+#endif

+

+#elif defined(STM32F401xx)

+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

+#define STM32_0WS_THRESHOLD         30000000

+#define STM32_1WS_THRESHOLD         60000000

+#define STM32_2WS_THRESHOLD         84000000

+#define STM32_3WS_THRESHOLD         0

+#define STM32_4WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

 #define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

+#define STM32_0WS_THRESHOLD         24000000

+#define STM32_1WS_THRESHOLD         48000000

+#define STM32_2WS_THRESHOLD         72000000

+#define STM32_3WS_THRESHOLD         84000000

+#define STM32_4WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

 #elif (STM32_VDD >= 210) && (STM32_VDD < 240)

 #define STM32_0WS_THRESHOLD         18000000

 #define STM32_1WS_THRESHOLD         36000000

 #define STM32_2WS_THRESHOLD         54000000

 #define STM32_3WS_THRESHOLD         72000000

-#define STM32_4WS_THRESHOLD         90000000

-#define STM32_5WS_THRESHOLD         108000000

-#define STM32_6WS_THRESHOLD         120000000

-#define STM32_7WS_THRESHOLD         138000000

+#define STM32_4WS_THRESHOLD         840000000

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

 #elif (STM32_VDD >= 180) && (STM32_VDD < 210)

 #define STM32_0WS_THRESHOLD         16000000

 #define STM32_1WS_THRESHOLD         32000000

 #define STM32_2WS_THRESHOLD         48000000

 #define STM32_3WS_THRESHOLD         64000000

-#define STM32_4WS_THRESHOLD         80000000

-#define STM32_5WS_THRESHOLD         96000000

-#define STM32_6WS_THRESHOLD         112000000

-#define STM32_7WS_THRESHOLD         128000000

+#define STM32_4WS_THRESHOLD         800000000

+#define STM32_5WS_THRESHOLD         840000000

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

 #else

 #error "invalid VDD voltage specified"

 #endif

 

-#else /* !defined(STM32F40XX) */

-#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)

+#else /* STM32F2XX */

+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

 #define STM32_0WS_THRESHOLD         30000000

 #define STM32_1WS_THRESHOLD         60000000

 #define STM32_2WS_THRESHOLD         90000000

@@ -681,7 +796,7 @@
 #else

 #error "invalid VDD voltage specified"

 #endif

-#endif /* !defined(STM32F40XX) */

+#endif /* STM32F2XX */

 

 /*

  * HSI related checks.

@@ -916,6 +1031,43 @@
 #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"

 #endif

 

+/* Calculating VOS settings, it is different for each sub-platform.*/

+#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \

+    defined(__DOXYGEN__)

+#if STM32_SYSCLK <= 120000000

+#define STM32_VOS                   STM32_VOS_SCALE3

+#define STM32_OVERDRIVE_REQUIRED    FALSE

+#elif STM32_SYSCLK <= 144000000

+#define STM32_VOS                   STM32_VOS_SCALE2

+#define STM32_OVERDRIVE_REQUIRED    FALSE

+#elif STM32_SYSCLK <= 168000000

+#define STM32_VOS                   STM32_VOS_SCALE1

+#define STM32_OVERDRIVE_REQUIRED    FALSE

+#else

+#define STM32_VOS                   STM32_VOS_SCALE1

+#define STM32_OVERDRIVE_REQUIRED    TRUE

+#endif

+

+#elif defined(STM32F40_41xxx)

+#if STM32_SYSCLK <= 144000000

+#define STM32_VOS                   STM32_VOS_SCALE2

+#else

+#define STM32_VOS                   STM32_VOS_SCALE1

+#endif

+#define STM32_OVERDRIVE_REQUIRED    FALSE

+

+#elif defined(STM32F401xx)

+#if STM32_SYSCLK <= 60000000

+#define STM32_VOS                   STM32_VOS_SCALE3

+#else

+#define STM32_VOS                   STM32_VOS_SCALE2

+#endif

+#define STM32_OVERDRIVE_REQUIRED    FALSE

+

+#else /* STM32F2XX */

+#define STM32_OVERDRIVE_REQUIRED    FALSE

+#endif

+

 /**

  * @brief   AHB frequency.

  */

@@ -1189,8 +1341,10 @@
 #define STM32_FLASHBITS             0x00000005

 #elif STM32_HCLK <= STM32_6WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000006

-#else

+#elif STM32_HCLK <= STM32_7WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000007

+#else

+#define STM32_FLASHBITS             0x00000008

 #endif

 

 /* There are differences in vector names in the various sub-families,

diff --git a/os/hal/ports/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32F4xx/stm32_registry.h
index ba462175c..5edcaad15 100644
--- a/os/hal/ports/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32F4xx/stm32_registry.h
@@ -25,10 +25,6 @@
 #ifndef _STM32_REGISTRY_H_

 #define _STM32_REGISTRY_H_

 

-#if defined(STM32F40XX) || defined(STM32F427X)

-#define STM32F4XX

-#endif

-

 /*===========================================================================*/

 /* Platform capabilities.                                                    */

 /*===========================================================================*/