AVR: add DMA low level driver for XMEGA128A4U

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11522 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 353 insertions, 0 deletions

diff --git a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/driver.mk b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/driver.mk
new file mode 100644
index 000000000..e4f348bb7
--- /dev/null
+++ b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/driver.mk
@@ -0,0 +1,15 @@
+

+# No need of the smart build for trhis file for the moment.

+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c

+

+PLATFORMINC += $(CHIBIOS)/os/hal/ports/AVR/XMEGA/LLD/DMAv1

+

+#ifeq ($(USE_SMART_BUILD),yes)

+#ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)

+#PLATFORMSRC += $(CHIBIOS)/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c

+#endif

+#else

+#PLATFORMSRC += $(CHIBIOS)/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/xmega_dma_lld.c

+#endif

+

+#PLATFORMINC += $(CHIBIOS)/os/hal/ports/AVR/XMEGA/LLD/DMAv1

diff --git a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c
new file mode 100644
index 000000000..4c49e92f4
--- /dev/null
+++ b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c
@@ -0,0 +1,200 @@
+/*

+    ChibiOS - Copyright (C) 2016..2018 Theodore Ateba

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    DMAv1/xmega_dma_lld.c

+ * @brief   AVR XMEGA DMA low level driver source file.

+ *

+ * @addtogroup DMA

+ * @{

+ */

+

+#include "hal.h"

+

+/*==========================================================================*/

+/* Driver exported variables.                                               */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* Driver local variables and types.                                        */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* Driver local functions.                                                  */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* Driver interrupt handlers.                                               */

+/*==========================================================================*/

+

+/**

+ * @brief   ISR for DMA channel 0.

+ *

+ * @param[in] DMA_CH0_vect  DMA controller channel0 interrupt vector.

+ */

+OSAL_IRQ_HANDLER(DMA_CH0_vect) {

+

+  OSAL_IRQ_PROLOGUE();

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   ISR for DMA channel 1.

+ *

+ * @param[in] DMA_CH1_vect  DMA controller channel1 interrupt vector.

+ */

+OSAL_IRQ_HANDLER(DMA_CH1_vect) {

+

+  OSAL_IRQ_PROLOGUE();

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   ISR for DMA channel 2.

+ *

+ * @param[in] DMA_CH2_vect  DMA controller channel2 interrupt vector.

+ */

+OSAL_IRQ_HANDLER(DMA_CH2_vect) {

+

+  OSAL_IRQ_PROLOGUE();

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   ISR for DMA channel 3.

+ *

+ * @param[in] DMA_CH3_vect  DMA controller channel3 interrupt vector.

+ */

+OSAL_IRQ_HANDLER(DMA_CH3_vect) {

+

+  OSAL_IRQ_PROLOGUE();

+  OSAL_IRQ_EPILOGUE();

+}

+

+/*==========================================================================*/

+/* Driver exported functions.                                               */

+/*==========================================================================*/

+

+

+

+// Optional reload of source and destination addresses at the end of each:

+// - Burst

+// - Block

+// - Tansaction

+

+// Optional interrupt at the end of transaction

+

+// Optional connection to CRC generator for CRC on DMA data

+

+// void dma_lld_set_transfer_src()  /* source.                */

+// void dma_lld_set_transfer_dst()  /* Destination.           */

+// void dma_lld_set_transfer_trg()  /* Trigger.               */

+// void dma_lld_set_transfer_siz()  /* Size. (1, 2, 4 or 8).  */

+

+// void dma_lld_read()

+// void dma_lld_write()

+// void isr_on_transfer_complate()

+// void dma_lld_set_double_buffer_mode()

+// void isr_on_error_during_tranfer()

+

+/**

+ * @brief   Enable DMA controller.

+ *

+ * @param[in] dmacp   pointer to the dma controller

+ */

+void dmaControllerEnable(DMA_t *dmacp) {

+

+  dmacp->CTRL |= DMA_ENABLE_bm;

+}

+

+/**

+ * @brief   Disable DMA controller.

+ * @note    On going transfers will be aborted.

+ *

+ * @param[in] dmacp   pointer to the dma controller

+ */

+void dmaControllerDisable(DMA_t *dmacp) {

+

+  dmacp->CTRL &= ~(DMA_ENABLE_bm);

+}

+

+/**

+ * @brief   Reset DMA controller.

+ * @pre     The DMA controller must be disabled before to process to a reset.

+ *

+ * @param[in] dmacp   pointer to the dma controller

+ */

+void damReset(void) {

+

+  DMA.CTRL &= ~DMA_ENABLE_bm;    /* Disable the DMA before a reset.      */

+  DMA.CTRL |= DMA_RESET_bm;      /* Perform the reset of the DMA module. */

+  while(DMA.CTRL & DMA_RESET_bm);   /* Wait until reset is complated.       */

+}

+

+/**

+ * @brief   Enable a DMA channel.

+ *

+ * @param[in] dmacp   pointer to the dma channel

+ */

+void dmaChannelEnable(DMA_CH_t *dmacp) {

+

+  dmacp->CTRLA |= DMA_CH_ENABLE_bm;

+}

+

+/**

+ * @brief   Disable a DMA channel.

+ *

+ * @param[in] dmacp   pointer to the dma channel

+ */

+void dmaChannelDisable(DMA_CH_t *dmacp) {

+

+  dmacp->CTRLA &= ~DMA_CH_ENABLE_bm;

+}

+

+/**

+ * @brief   Disable a DMA channel.

+ * @note    This can only be done if the DMA channel is disable.

+ *

+ * @param[in] dmacp   pointer to the dma channel

+ */

+void dmaChannelReset(DMA_CH_t *dmacp) {

+

+}

+

+void dmaEnableSingleShot(DMA_CH_t * dmacp ) {

+

+	dmacp->CTRLA |= DMA_CH_SINGLE_bm;

+}

+

+void dmaDisableSingleShot(DMA_CH_t * dmacp ) {

+

+	dmacp->CTRLA &= ~DMA_CH_SINGLE_bm;

+}

+

+void dmaSetTriggerSource(DMA_CH_t * dmacp, uint8_t trigger) {

+

+	dmacp->TRIGSRC = trigger;

+}

+

+void dmaStartTransfer(DMA_CH_t * dmacp) {

+

+	dmacp->CTRLA |= DMA_CH_TRFREQ_bm;

+}

+

+//#endif /* HAL_USE_DMA */

+

+/** @} */

+

diff --git a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h
new file mode 100644
index 000000000..5ffd1ec14
--- /dev/null
+++ b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h
@@ -0,0 +1,138 @@
+/*

+    ChibiOS - Copyright (C) 2016..2018 Theodore Ateba

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    DMAv1/xmega_dma_lld.h

+ * @brief   AVR XMEGA DMA low level driver header file.

+ *

+ * @addtogroup DMA

+ * @{

+ */

+

+#ifndef XMEGA_DMA_LLD_H

+#define XMEGA_DMA_LLD_H

+

+/*==========================================================================*/

+/* Driver constants.                                                        */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* Driver pre-compile time settings.                                        */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* Derived constants and error checks.                                      */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* Driver data structures and types.                                        */

+/*==========================================================================*/

+

+

+/**

+ * @brief   Programmable channel priority

+ */

+

+/**

+ * @brief   DMA channels index

+ */

+typedef enum {

+  DMA_CHANNEL0 = 0, /**< DMA channel 0. */

+  DMA_CHANNEL1 = 1, /**< DMA channel 1. */

+  DMA_CHANNEL2 = 2, /**< DMA channel 2. */

+  DMA_CHANNEL3 = 3, /**< DMA channel 3. */

+} dmachannelid_t;

+

+/**

+ * @brief   DMA possible addressing modes.

+ */

+typedef enum {

+  DMA_ADDRMODE_STATIC = 0, /* Static addressing mode.       */

+  DMA_ADDRMODE_INCRE  = 1, /* Incremental addressing mode.  */

+  DMA_ADDRMODE_DECRE  = 2, /* Decremental addressing mode.  */

+} dmaaddrmode_t;

+

+/**

+ * @brief   DMA possible double buffer modes settings.

+ */

+typedef enum {

+  DMA_DBUFMODE_DISABLE  = 0, /* No double buffer enabled.                   */

+  DMA_DBUFMODE_CH01     = 1, /* Double buffer enabled on channel01.         */

+  DMA_DBUFMODE_CH23     = 2, /* Double buffer enabled on channel23.         */

+  DMA_DBUFMODE_CH01CH23 = 3, /* Double buffer enabled on channe01 and 2/3.  */

+} dmadbufmode_t;

+

+/**

+ * @brief   DMA possible channel burst mode.

+ */

+typedef enum {

+  DMA_BURSTMODE_1BYTE = 0,  /* Burst mode is 1 byte.                        */

+  DMA_BURSTMODE_2BYTE = 1,  /* Burst mode is 2 byte.                        */

+  DMA_BURSTMODE_4BYTE = 2,  /* Burst mode is 4 byte.                        */

+  DMA_BURSTMODE_8BYTE = 3,  /* Burst mode is 8 byte.                        */

+} dmachannelburstmode_t;

+

+/*==========================================================================*/

+/* Driver macros.                                                           */

+/*==========================================================================*/

+

+/*==========================================================================*/

+/* External declarations.                                                   */

+/*==========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+void damReset(void);

+void dmaConfigDoubleBuffering(DMA_DBUFMODE_t dbufMode);

+void dmaSetPriority(DMA_PRIMODE_t priMode);

+uint8_t dmaChannelIsOngoing(DMA_CH_t * channel);

+uint8_t dmaIsOngoing(void);

+uint8_t dmaChannelIsPending(DMA_CH_t * channel);

+uint8_t dmaIsPending(void);

+uint8_t dmaReturnStatusNonBlocking(DMA_CH_t * channel);

+uint8_t dmaReturnStatusBlocking(DMA_CH_t * channel);

+

+void dmaChannelEnable(DMA_CH_t * channel);

+void dmaChannelDisable(DMA_CH_t * channel);

+void dmaChannelReset(DMA_CH_t * channel);

+void dmaSetIntLevel(DMA_CH_t * channel,

+                      DMA_CH_TRNINTLVL_t transferInt,

+                      DMA_CH_ERRINTLVL_t errorInt);

+void dmaSetupBlock(DMA_CH_t * channel,

+                     const void * srcAddr,

+                     DMA_CH_SRCRELOAD_t srcReload,

+                     DMA_CH_SRCDIR_t srcDirection,

+                     void * destAddr,

+                     DMA_CH_DESTRELOAD_t destReload,

+                     DMA_CH_DESTDIR_t destDirection,

+                     uint16_t blockSize,

+                     DMA_CH_BURSTLEN_t burstMode,

+                     uint8_t repeatCount,

+                     bool useRepeat);

+void dmaEnableSingleShot(DMA_CH_t * channel);

+void dmaDisableSingleShot(DMA_CH_t * channel);

+void dmaSetTriggerSource(DMA_CH_t * channel, uint8_t trigger);

+void dmaStartTransfer(DMA_CH_t * channel);

+

+#ifdef __cplusplus

+}

+#endif

+//#endif /* HAL_USE_DMA */

+

+#endif /* XMEGA_DMA_LLD_H */

+

+/** @} */