git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6440 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 41 insertions, 14 deletions

diff --git a/os/hal/ports/STM32F4xx/hal_lld.c b/os/hal/ports/STM32F4xx/hal_lld.c
index e414043cc..7aeb67297 100644
--- a/os/hal/ports/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32F4xx/hal_lld.c
@@ -22,8 +22,6 @@
  * @{

  */

 

-/* TODO: LSEBYP like in F3.*/

-

 #include "hal.h"

 

 /*===========================================================================*/

@@ -60,7 +58,13 @@ static void hal_lld_backup_domain_init(void) {
   }

 

 #if STM32_LSE_ENABLED

+#if defined(STM32_LSE_BYPASS)

+  /* LSE Bypass.*/

+  RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

+#else

+  /* No LSE Bypass.*/

   RCC->BDCR |= RCC_BDCR_LSEON;

+#endif

   while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

     ;                                       /* Waits until LSE is stable.   */

 #endif

@@ -142,17 +146,19 @@ void stm32_clock_init(void) {
   /* PWR initialization.*/

 #if defined(STM32F4XX) || defined(__DOXYGEN__)

   PWR->CR = STM32_VOS;

-  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)

-    ;                           /* Waits until power regulator is stable.   */

 #else

   PWR->CR = 0;

 #endif

 

-  /* Initial clocks setup and wait for HSI stabilization, the MSI clock is

-     always enabled because it is the fallback clock when PLL the fails.*/

-  RCC->CR |= RCC_CR_HSION;

-  while ((RCC->CR & RCC_CR_HSIRDY) == 0)

-    ;                           /* Waits until HSI is stable.               */

+  /* HSI setup, it enforces the reset situation in order to handle possible

+     problems with JTAG probes and re-initializations.*/

+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

+  while (!(RCC->CR & RCC_CR_HSIRDY))

+    ;                                       /* Wait until HSI is stable.    */

+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

+  RCC->CFGR = 0;                            /* CFGR reset value.            */

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Waits until HSI is selected. */

 

 #if STM32_HSE_ENABLED

   /* HSE activation.*/

@@ -179,21 +185,42 @@ void stm32_clock_init(void) {
   RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |

                  STM32_PLLM;

   RCC->CR |= RCC_CR_PLLON;

+

+  /* Synchronization with voltage regulator stabilization.*/

+#if defined(STM32F4XX)

+  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)

+    ;                           /* Waits until power regulator is stable.   */

+

+#if STM32_OVERDRIVE_REQUIRED

+  /* Overdrive activation performed after activating the PLL in order to save

+     time as recommended in RM in "Entering Over-drive mode" paragraph.*/

+  PWR->CR |= PWR_CR_ODEN;

+  while (!(PWR->CSR & PWR_CSR_ODRDY))

+      ;

+  PWR->CR |= PWR_CR_ODSWEN;

+  while (!(PWR->CSR & PWR_CSR_ODSWRDY))

+      ;

+#endif /* STM32_OVERDRIVE_REQUIRED */

+#endif /* defined(STM32F4XX) */

+

+  /* Waiting for PLL lock.*/

   while (!(RCC->CR & RCC_CR_PLLRDY))

-    ;                           /* Waits until PLL is stable.               */

-#endif

+    ;

+#endif /* STM32_OVERDRIVE_REQUIRED */

 

 #if STM32_ACTIVATE_PLLI2S

   /* PLLI2S activation.*/

   RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;

   RCC->CR |= RCC_CR_PLLI2SON;

+

+  /* Waiting for PLL lock.*/

   while (!(RCC->CR & RCC_CR_PLLI2SRDY))

-    ;                           /* Waits until PLLI2S is stable.            */

+    ;

 #endif

 

   /* Other clock-related settings (dividers, MCO etc).*/

-  RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

-               STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;

+  RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

+              STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;

 

   /* Flash setup.*/

 #if defined(STM32_USE_REVISION_A_FIX)