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author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-15 09:19:43 +0000 |
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committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-15 09:19:43 +0000 |
commit | 0aa3fea6042e656743fc5206f9e06373ddbc29f0 (patch) | |
tree | 1bce73086822a22a3cb512207e56113a373546f5 /os/hal/ports/STM32 | |
parent | 88d9233985b932ad12b54af44a7496a14145f17c (diff) | |
download | ChibiOS-0aa3fea6042e656743fc5206f9e06373ddbc29f0.tar.gz ChibiOS-0aa3fea6042e656743fc5206f9e06373ddbc29f0.tar.bz2 ChibiOS-0aa3fea6042e656743fc5206f9e06373ddbc29f0.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8602 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32')
-rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 8b8a7f267..c610f0c98 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -293,9 +293,9 @@ * @name PWR_CR register bits definitions
* @{
*/
-#define STM32_VOS_SCALE3 (PWR_CR_VOS_0)
-#define STM32_VOS_SCALE2 (PWR_CR_VOS_1)
-#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0)
+#define STM32_VOS_SCALE3 0x00004000
+#define STM32_VOS_SCALE2 0x00008000
+#define STM32_VOS_SCALE1 0x0000C000
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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