From 0aa3fea6042e656743fc5206f9e06373ddbc29f0 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 15 Dec 2015 09:19:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8602 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F4xx/hal_lld.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'os/hal/ports/STM32') diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 8b8a7f267..c610f0c98 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -293,9 +293,9 @@ * @name PWR_CR register bits definitions * @{ */ -#define STM32_VOS_SCALE3 (PWR_CR_VOS_0) -#define STM32_VOS_SCALE2 (PWR_CR_VOS_1) -#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0) +#define STM32_VOS_SCALE3 0x00004000 +#define STM32_VOS_SCALE2 0x00008000 +#define STM32_VOS_SCALE1 0x0000C000 #define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ #define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ #define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ -- cgit v1.2.3