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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-03-03 08:41:56 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-03-03 08:41:56 +0000 |
| commit | 8e47415958cd7ca27a36e0ab926bc437950b975e (patch) | |
| tree | c73461ebe2b110cbaf41d9436385387cadaa420d /os/hal/ports/STM32/STM32L4xx | |
| parent | 65ad4b649437f1635543578a6f257451253287e0 (diff) | |
| download | ChibiOS-8e47415958cd7ca27a36e0ab926bc437950b975e.tar.gz ChibiOS-8e47415958cd7ca27a36e0ab926bc437950b975e.tar.bz2 ChibiOS-8e47415958cd7ca27a36e0ab926bc437950b975e.zip | |
Fixed bug #818.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10116 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L4xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index bb7ccc69d..f02d2a3ba 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -156,7 +156,11 @@ void stm32_clock_init(void) { #if !STM32_NO_INIT
/* PWR clock enable.*/
- RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
+#else
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
+#endif
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 476c288be..d78b157f2 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -72,7 +72,7 @@ * @{
*/
#define STM32_HSI16CLK 16000000 /**< High speed internal clock. */
-#define STM32_LSICLK 38000 /**< Low speed internal clock. */
+#define STM32_LSICLK 32000 /**< Low speed internal clock. */
/** @} */
/**
|