From 8e47415958cd7ca27a36e0ab926bc437950b975e Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 3 Mar 2017 08:41:56 +0000 Subject: Fixed bug #818. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10116 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32L4xx/hal_lld.c | 6 +++++- os/hal/ports/STM32/STM32L4xx/hal_lld.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'os/hal/ports/STM32/STM32L4xx') diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index bb7ccc69d..f02d2a3ba 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -156,7 +156,11 @@ void stm32_clock_init(void) { #if !STM32_NO_INIT /* PWR clock enable.*/ - RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN; +#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN) + RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN; +#else + RCC->APB1ENR1 = RCC_APB1ENR1_PWREN; +#endif /* Initial clocks setup and wait for MSI stabilization, the MSI clock is always enabled because it is the fall back clock when PLL the fails. diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 476c288be..d78b157f2 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -72,7 +72,7 @@ * @{ */ #define STM32_HSI16CLK 16000000 /**< High speed internal clock. */ -#define STM32_LSICLK 38000 /**< Low speed internal clock. */ +#define STM32_LSICLK 32000 /**< Low speed internal clock. */ /** @} */ /** -- cgit v1.2.3