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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-11-30 09:49:53 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-11-30 09:49:53 +0000 |
| commit | f35ebd89d421105e8449d94c2bc80d81000e8246 (patch) | |
| tree | b26216c6129c9c14b11fddf864caf7f10370bcf6 /os/hal/ports/STM32/STM32L4xx/hal_lld.c | |
| parent | 17ed462d6f884883e5b0552dba582d4e9a30e7da (diff) | |
| download | ChibiOS-f35ebd89d421105e8449d94c2bc80d81000e8246.tar.gz ChibiOS-f35ebd89d421105e8449d94c2bc80d81000e8246.tar.bz2 ChibiOS-f35ebd89d421105e8449d94c2bc80d81000e8246.zip | |
Added STM32L496xx/STM32L4A6xx support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11089 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L4xx/hal_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index d87f9b336..5b6be0999 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -253,12 +253,20 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
/* PLLM and PLLSRC are common to all PLLs.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR |
+ STM32_PLLREN | STM32_PLLQ |
+ STM32_PLLQEN | STM32_PLLP |
+ STM32_PLLPEN | STM32_PLLN |
+ STM32_PLLM | STM32_PLLSRC;
+#else
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
+#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
@@ -271,10 +279,17 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
+ STM32_PLLSAI1REN | STM32_PLLSAI1Q |
+ STM32_PLLSAI1QEN | STM32_PLLSAI1P |
+ STM32_PLLSAI1PEN | STM32_PLLSAI1N;
+#else
RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
STM32_PLLSAI1P | STM32_PLLSAI1PEN |
STM32_PLLSAI1N;
+#endif
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL lock.*/
@@ -284,9 +299,15 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLLSAI2
/* PLLSAI2 activation.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
+ STM32_PLLSAI2REN | STM32_PLLSAI2P |
+ STM32_PLLSAI2PEN | STM32_PLLSAI2N;
+#else
RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
STM32_PLLSAI2P | STM32_PLLSAI2PEN |
STM32_PLLSAI2N;
+#endif
RCC->CR |= RCC_CR_PLLSAI2ON;
/* Waiting for PLL lock.*/
|