diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-11-30 09:49:53 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-11-30 09:49:53 +0000 |
| commit | f35ebd89d421105e8449d94c2bc80d81000e8246 (patch) | |
| tree | b26216c6129c9c14b11fddf864caf7f10370bcf6 | |
| parent | 17ed462d6f884883e5b0552dba582d4e9a30e7da (diff) | |
| download | ChibiOS-f35ebd89d421105e8449d94c2bc80d81000e8246.tar.gz ChibiOS-f35ebd89d421105e8449d94c2bc80d81000e8246.tar.bz2 ChibiOS-f35ebd89d421105e8449d94c2bc80d81000e8246.zip | |
Added STM32L496xx/STM32L4A6xx support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11089 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld | 85 | ||||
| -rw-r--r-- | os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h | 7 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 21 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 42 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 424 | ||||
| -rw-r--r-- | readme.txt | 1 |
6 files changed, 576 insertions, 4 deletions
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld new file mode 100644 index 000000000..606c59c95 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L496xG memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 256k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 64k /* This memory also mapped at address 0x20040000 */
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h b/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h index 95a4f5f7e..fbb304fe6 100644 --- a/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h +++ b/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h @@ -48,7 +48,11 @@ * @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+#define CORTEX_NUM_VECTORS 96
+#else
#define CORTEX_NUM_VECTORS 88
+#endif
/* The following code is not processed when the file is included from an
asm module.*/
@@ -59,7 +63,8 @@ definition compatible with the vendor include file.*/
#if !defined(STM32L471xx) && !defined(STM32L475xx) && \
!defined(STM32L476xx) && !defined(STM32L485xx) && \
- !defined (STM32L486xx)
+ !defined(STM32L486xx) && !defined(STM32L496xx) && \
+ !defined(STM32L4A6xx)
#include "board.h"
#endif
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index d87f9b336..5b6be0999 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -253,12 +253,20 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
/* PLLM and PLLSRC are common to all PLLs.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR |
+ STM32_PLLREN | STM32_PLLQ |
+ STM32_PLLQEN | STM32_PLLP |
+ STM32_PLLPEN | STM32_PLLN |
+ STM32_PLLM | STM32_PLLSRC;
+#else
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
+#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
@@ -271,10 +279,17 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
+ STM32_PLLSAI1REN | STM32_PLLSAI1Q |
+ STM32_PLLSAI1QEN | STM32_PLLSAI1P |
+ STM32_PLLSAI1PEN | STM32_PLLSAI1N;
+#else
RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
STM32_PLLSAI1P | STM32_PLLSAI1PEN |
STM32_PLLSAI1N;
+#endif
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL lock.*/
@@ -284,9 +299,15 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLLSAI2
/* PLLSAI2 activation.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
+ STM32_PLLSAI2REN | STM32_PLLSAI2P |
+ STM32_PLLSAI2PEN | STM32_PLLSAI2N;
+#else
RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
STM32_PLLSAI2P | STM32_PLLSAI2PEN |
STM32_PLLSAI2N;
+#endif
RCC->CR |= RCC_CR_PLLSAI2ON;
/* Waiting for PLL lock.*/
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 8d7fa1901..81826c5ac 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -49,10 +49,10 @@ */
#if defined(STM32L432xx) || defined(STM32L471xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || \
- defined(__DOXYGEN__)
+ defined(STM32L496xx) || defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
-#elif defined(STM32L485xx) || defined(STM32L486xx)
+#elif defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
#define PLATFORM_NAME "STM32L4xx Ultra Low Power with Crypto"
#else
@@ -166,6 +166,7 @@ #define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
+#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
@@ -1236,6 +1237,18 @@ #error "invalid STM32_PLLR_VALUE value specified"
#endif
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/**
+ * @brief STM32_PLLPDIV field. (Only for STM32L496xx/4A6xx)
+ */
+#if ((STM32_PLLPDIV_VALUE != 1) && (STM32_PLLPDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLPDIV_VALUE value specified"
+#endif
+#endif
+
/**
* @brief STM32_PLLPEN field.
*/
@@ -1527,6 +1540,18 @@ #error "invalid STM32_PLLSAI1R_VALUE value specified"
#endif
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/**
+ * @brief STM32_PLLSAI1PDIV field. (Only for STM32L496xx/4A6xx)
+ */
+#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI1PDIV (STM32_PLLSAI1PDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
+#endif
+#endif
+
/**
* @brief STM32_PLLSAI1PEN field.
*/
@@ -1670,6 +1695,18 @@ #error "invalid STM32_PLLSAI2R_VALUE value specified"
#endif
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/**
+ * @brief STM32_PLLSAI2PDIV field. (Only for STM32L496xx/4A6xx)
+ */
+#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI2PDIV (STM32_PLLSAI2PDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
+#endif
+#endif
+
/**
* @brief STM32_PLLSAI2PEN field.
*/
@@ -2090,7 +2127,6 @@ #include "nvic.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
-#include "stm32_isr.h"
#ifdef __cplusplus
extern "C" {
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 44364d60c..bd195d1db 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -31,6 +31,8 @@ #elif defined(STM32L476xx)
#define STM32L476xx
+#elif defined(STM32L496xx)
+#define STM32L496xx
#else
#error "STM32L4xx device not specified"
#endif
@@ -766,6 +768,428 @@ #endif /* defined(STM32L476xx) */
+/*===========================================================================*/
+/* STM32L496xx. */
+/*===========================================================================*/
+
+#if defined(STM32L496xx)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
+#define STM32_HAS_CAN2 TRUE
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_CAN2_TX_HANDLER Vector198
+#define STM32_CAN2_RX0_HANDLER Vector19C
+#define STM32_CAN2_RX1_HANDLER Vector1A0
+#define STM32_CAN2_SCE_HANDLER Vector1A4
+#define STM32_CAN2_TX_NUMBER 86
+#define STM32_CAN2_RX0_NUMBER 87
+#define STM32_CAN2_RX1_NUMBER 88
+#define STM32_CAN2_SCE_NUMBER 89
+
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 7
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH6_HANDLER Vector150
+#define STM32_DMA2_CH7_HANDLER Vector154
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+#define STM32_DMA2_CH6_NUMBER 68
+#define STM32_DMA2_CH7_NUMBER 69
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 39
+#define STM32_EXTI_IMR_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+#define STM32_EXTI_LINE0_HANDLER Vector58
+#define STM32_EXTI_LINE1_HANDLER Vector5C
+#define STM32_EXTI_LINE2_HANDLER Vector60
+#define STM32_EXTI_LINE3_HANDLER Vector64
+#define STM32_EXTI_LINE4_HANDLER Vector68
+#define STM32_EXTI_LINE5_9_HANDLER Vector9C
+#define STM32_EXTI_LINE10_15_HANDLER VectorE0
+#define STM32_EXTI_LINE1635_38_HANDLER Vector44
+#define STM32_EXTI_LINE18_HANDLER VectorE4
+#define STM32_EXTI_LINE19_HANDLER Vector48
+#define STM32_EXTI_LINE20_HANDLER Vector4C
+#define STM32_EXTI_LINE2122_HANDLER Vector140
+
+#define STM32_EXTI_LINE0_NUMBER 6
+#define STM32_EXTI_LINE1_NUMBER 7
+#define STM32_EXTI_LINE2_NUMBER 8
+#define STM32_EXTI_LINE3_NUMBER 9
+#define STM32_EXTI_LINE4_NUMBER 10
+#define STM32_EXTI_LINE5_9_NUMBER 23
+#define STM32_EXTI_LINE10_15_NUMBER 40
+#define STM32_EXTI_LINE1635_38_NUMBER 1
+#define STM32_EXTI_LINE18_NUMBER 41
+#define STM32_EXTI_LINE19_NUMBER 2
+#define STM32_EXTI_LINE20_NUMBER 3
+#define STM32_EXTI_LINE2122_NUMBER 64
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOFEN | \
+ RCC_AHB2ENR_GPIOGEN | \
+ RCC_AHB2ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00030000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00003000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_ERROR_NUMBER 73
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C4 TRUE
+#define STM32_I2C4_EVENT_HANDLER Vector18C
+#define STM32_I2C4_EVENT_NUMBER 83
+#define STM32_I2C4_ERROR_HANDLER Vector190
+#define STM32_I2C4_ERROR_NUMBER 84
+#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_I2C4_RX_DMA_CHN 0x00000000
+#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_I2C4_TX_DMA_CHN 0x00000000
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector15C
+#define STM32_QUADSPI1_NUMBER 71
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDMMC1_HANDLER Vector104
+#define STM32_SDMMC1_NUMBER 49
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_SPI2_RX_DMA_CHN 0x00001000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x00010000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM2_NUMBER 28
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM3_NUMBER 29
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM4_NUMBER 30
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM5_NUMBER 50
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM6_NUMBER 54
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM7_NUMBER 55
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_CC_HANDLER VectorF8
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_CC_NUMBER 46
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+#define STM32_TIM15_HANDLER VectorA0
+#define STM32_TIM15_NUMBER 24
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_HANDLER VectorA4
+#define STM32_TIM16_NUMBER 25
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_HANDLER VectorA8
+#define STM32_TIM17_NUMBER 26
+
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART1_NUMBER 37
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART2_NUMBER 38
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_USART3_NUMBER 39
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000200
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART4_NUMBER 52
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
+#define STM32_UART4_RX_DMA_CHN 0x00020000
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
+#define STM32_UART4_TX_DMA_CHN 0x00000200
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_HANDLER Vector114
+#define STM32_UART5_NUMBER 53
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
+#define STM32_UART5_RX_DMA_CHN 0x00000020
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
+#define STM32_UART5_TX_DMA_CHN 0x00000002
+
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER Vector158
+#define STM32_LPUART1_NUMBER 70
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+#define STM32_OTG1_HANDLER Vector14C
+#define STM32_OTG1_NUMBER 67
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+#define STM32_DMA2D_HANDLER Vector1A8
+#define STM32_DMA2D_NUMBER 90
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L496xx) */
+
/** @} */
#endif /* STM32_REGISTRY_H */
diff --git a/readme.txt b/readme.txt index 0bc754840..ee7e7e975 100644 --- a/readme.txt +++ b/readme.txt @@ -89,6 +89,7 @@ *****************************************************************************
*** Next ***
+- NEW: Added STM32L496xx/STM32L4A6xx support.
- NEW: Added STM32F030x4 support.
- NEW: Added a Managed Flash Storage module to the HAL.
- NEW: Modified the STM32 OTGv1 driver to work without pump thread, transfers
|